Document Outline

• SerialLite II MegaCore Function User Guide
  • Contents
  • 1. About This MegaCore Function
    • Release Information
    • Device Family Support
    • Features
    • General Description
    • Performance and Resource Utilization
    • Installation and Licensing
      • OpenCore Plus Evaluation
      • OpenCore Plus Time-Out Behavior
  • 2. Getting Started
    • Design Flow
      • Create a New Quartus II Project
      • Launch the MegaWizard Plug-In Manager
    • Parameterize
      • Set Up Simulation
      • Generate Files
    • Simulate the Design
    • Instantiate the MegaCore
    • Specify Constraints
      • Assign Virtual Pins
      • Fitter Constraints
      • Timing Constraints
    • Compile and Program
  • 3. Parameter Settings
    • Link Consistency
    • Physical Layer Configuration
      • Data Rate
      • Transfer size
      • Reference Clock Frequency
      • Port Type
      • Self Synchronized Link Up
      • Number of Lanes
      • Scramble
      • De-Scramble
      • Broadcast Mode
      • Clock Compensation
      • Lane Polarity and Order Reversal
        • Lane Polarity
        • Lane Order
        • Frequency Offset Tolerance
    • Link Layer Configuration
      • Data Type:Packets
      • Data Type:Streaming
      • Regular Data Port
      • Priority Port
        • Retry-on-error Disabled
        • Retry-on-error Enabled
        • Segment Size
      • Retry-on-error
        • Retry-on-error Responses
        • Retry-on-error Operation Example
      • Flow Control
        • Flow Control Operation
        • Flow Control Operation Example
        • Selecting the Proper Threshold Value
        • Selecting the Proper Pause Duration
        • External Flow Control (When RX FIFO Size is 0)
      • Transmit/Receive FIFO Buffers
        • FIFO Buffer Size
        • FIFO Buffer Structure
      • Data Integrity Protection: CRC
        • 16-Bit Versus 32-Bit CRC
    • Transceiver Configuration
      • Voltage Output Differential (VOD) Control Settings
      • Pre-Emphasis Control Settings
      • Transmitter Buffer Power (VCCH)
      • Equalizer Control Settings
      • Bandwidth Mode
      • Starting Channel number
      • Instantiating a Transceiver Reconfiguration Block
      • ALTGX Support Signals
    • Error Handling
    • Optimizing the Implementation
      • Improving Performance
        • Feature Selection
        • Running Different Seeds
        • Limiting Fanout
        • Floorplanning
      • Minimizing Logic Utilization
      • Minimizing Memory Utilization
  • 4. Functional Description
    • Interface Overview
      • Atlantic Interface
      • High-Speed Serial Interface
    • Clocks and Data Rates
      • Aggregate Bandwidth
      • External Clock Modes
      • SerialLite II Internal Clocking Configurations
      • SerialLite II Deskew Support
      • SerialLite II Clocking Structure
        • Arria V, Cyclone V, and Stratix V Transceiver Clocking
      • SerialLite II MegaCore Pin-Out Diagrams
      • Initialization and Restart
    • Multiple Core Configuration
    • MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices
      • Design Consideration
        • Compilation
        • Testbench
        • Simulation Support
      • Parameter Settings For SerialLite II MegaCore and Custom PHY IP Core
      • Extra Signals Between SerialLite II MegaCore and Custom PHY IP Core
    • Signals
    • MegaCore Verification
  • 5. Testbench
    • General Description
      • Features
      • SerialLite II Testbench Files
    • Testbench Specifications
    • Simulation Flow
      • Running a Simulation
      • Simulation Pass and Fail Conditions
      • Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench)
      • Testbench Time-Out
      • Special Simulation Configuration Settings
      • Atlantic Receiver Behavior
    • Testbench Components Description
      • DUT
      • SISTER
      • AGEN
        • Verilog HDL
        • VHDL
      • AMON
        • Verilog HDL
        • VHDL
      • Status Monitors (pin_mon)
        • Pin_mon Tasks - Verilog HDL
      • Clock and Reset Generator
      • Custom PHY IP Core
    • Example Testbench – Verilog HDL
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions