Document Outline

• Triple-Speed Ethernet MegaCore Function User Guide
• Contents
• 1. About This MegaCore Function
  • About This MegaCore Function
  • Device Family Support
  • Features
  • 10/100/1000 Ethernet MAC Versus Small MAC
  • High-Level Block Diagrams
  • Example Applications
  • MegaCore Verification
    • Optical Platform
    • Copper Platform
  • Performance and Resource Utilization
  • Release Information
• 2. Getting Started with Altera IP Cores
  • Introduction to Altera IP Cores
  • Installing and Licensing IP Cores
  • OpenCore Plus IP Evaluation
  • Upgrading Outdated IP Cores
  • IP Catalog and Parameter Editor
    • Using the Parameter Editor
  • Design Walkthrough
    • Creating a New Quartus II Project
    • Specifying IP Core Parameters and Options
    • Generating a Design Example or Simulation Model
    • Simulate the System
    • Compiling the Triple-Speed Ethernet MegaCore Function Design
    • Programming an FPGA Device
  • Generated Files
    • Design Constraint File No Longer Generated
• 3. Parameter Settings
  • Parameter Settings
  • Core Configuration
  • Ethernet MAC Options
  • FIFO Options
  • Timestamp Options
  • PCS/Transceiver Options
• 4. Functional Description
  • 10/100/1000 Ethernet MAC
    • MAC Architecture
    • MAC Interfaces
    • MAC Transmit Datapath
      • IP Payload Re-alignment
      • Address Insertion
      • Frame Payload Padding
      • CRC-32 Generation
      • Interpacket Gap Insertion
      • Collision Detection in Half-Duplex Mode
    • MAC Receive Datapath
      • Preamble Processing
      • Collision Detection in Half-Duplex Mode
      • Address Checking
        • Unicast Address Checking
        • Multicast Address Resolution
      • Frame Type Validation
      • Payload Pad Removal
      • CRC Checking
      • Length Checking
      • Frame Writing
      • IP Payload Alignment
    • MAC Transmit and Receive Latencies
    • FIFO Buffer Thresholds
      • Receive Thresholds
      • Transmit Thresholds
      • Transmit FIFO Buffer Underflow
    • Congestion and Flow Control
      • Remote Device Congestion
      • Receive FIFO Buffer and Local Device Congestion
    • Magic Packets
      • Sleep Mode
      • Magic Packet Detection
    • MAC Local Loopback
    • MAC Error Correction Code
    • MAC Reset
    • PHY Management (MDIO)
      • MDIO Connection
      • MDIO Frame Format
    • Connecting MAC to External PHYs
      • Gigabit Ethernet
      • Programmable 10/100 Ethernet
      • Programmable 10/100/1000 Ethernet Operation
  • 1000BASE-X/SGMII PCS With Optional Embedded PMA
    • 1000BASE-X/SGMII PCS Architecture
    • Transmit Operation
      • Frame Encapsulation
      • 8b/10b Encoding
    • Receive Operation
      • Comma Detection
      • 8b/10b Decoding
      • Frame De-encapsulation
      • Synchronization
      • Carrier Sense
      • Collision Detection
    • Transmit and Receive Latencies
    • SGMII Converter
      • Transmit
      • Receive
    • Auto-Negotiation
      • 1000BASE-X Auto-Negotiation
      • SGMII Auto-Negotiation
    • Ten-bit Interface
    • PHY Loopback
    • PHY Power-Down
      • Power-Down in PCS Variations with Embedded PMA
    • 1000BASE-X/SGMII PCS Reset
  • Altera IEEE 1588v2 Feature
    • IEEE 1588v2 Supported Configurations
    • IEEE 1588v2 Features
    • IEEE 1588v2 Architecture
    • IEEE 1588v2 Transmit Datapath
    • IEEE 1588v2 Receive Datapath
    • IEEE 1588v2 Frame Format
      • PTP Frame in IEEE 802.3
      • PTP Frame over UDP/IPv4
      • PTP Frame over UDP/IPv6
• 5. Triple-Speed Ethernet with IEEE 1588v2 Design Example
  • Software Requirements
  • Triple-Speed Ethernet with IEEE 1588v2 Design Example Components
    • Base Addresses
  • Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files
  • Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design
  • Triple-Speed Ethernet with IEEE 1588v2 Testbench
    • Triple-Speed Ethernet with IEEE 1588v2 Testbench Files
    • Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow
    • Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Simulator
• 6. Configuration Register Space
  • MAC Configuration Register Space
    • Base Configuration Registers (Dword Offset 0x00 – 0x17)
      • Command_Config Register (Dword Offset 0x02)
    • Statistics Counters (Dword Offset 0x18 – 0x38)
    • Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
    • Supplementary Address (Dword Offset 0xC0 – 0xC7)
    • IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
    • IEEE 1588v2 Feature PMA Delay
  • PCS Configuration Register Space
    • Control Register (Word Offset 0x00)
    • Status Register (Word Offset 0x01)
    • Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)
      • 1000BASE-X
      • SGMII MAC Mode Auto Negotiation
      • SGMII PHY Mode Auto Negotiation
    • An_Expansion Register (Word Offset 0x06)
    • If_Mode Register (Word Offset 0x14)
  • Register Initialization
    • Triple-Speed Ethernet System with MII/GMII or RGMII
    • Triple-Speed Ethernet System with SGMII
    • Triple-Speed Ethernet System with 1000BASE-X Interface
• 7. Interface Signals
  • Interface Signals
    • 10/100/1000 Ethernet MAC Signals
      • Clock and Reset Signal
      • MAC Control Interface Signals
      • MAC Status Signals
      • MAC Receive Interface Signals
      • MAC Transmit Interface Signals
      • Pause and Magic Packet Signals
      • MII/GMII/RGMII Signals
      • PHY Management Signals
      • ECC Status Signals
    • 10/100/1000 Multiport Ethernet MAC Signals
      • Multiport MAC Clock and Reset Signals
      • Multiport MAC Receive Interface Signals
      • Multiport MAC Transmit Interface Signals
      • Multiport MAC Packet Classification Signals
      • Multiport MAC FIFO Status Signals
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
      • TBI Interface Signals
      • Status LED Control Signals
      • SERDES Control Signals
      • Arria 10 Transceiver Native PHY Signals
      • ECC Status Signals
    • 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
    • 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
      • 1.25 Gbps Serial Interface
      • Transceiver Native PHY Signal
      • SERDES Control Signals
    • 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
      • IEEE 1588v2 RX Timestamp Signals
      • IEEE 1588v2 TX Timestamp Signals
      • IEEE 1588v2 TX Timestamp Request Signals
      • IEEE 1588v2 TX Insert Control Timestamp Signals
      • IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
      • IEEE 1588v2 PCS Phase Measurement Clock Signal
      • IEEE 1588v2 PHY Path Delay Interface Signals
    • 1000BASE-X/SGMII PCS Signals
      • PCS Control Interface Signals
      • PCS Reset Signals
      • MII/GMII Clocks and Clock Enablers
      • GMII
      • MII
      • SGMII Status Signals
    • 1000BASE-X/SGMII PCS and PMA Signals
  • Timing
    • Avalon-ST Receive Interface
    • Avalon-ST Transmit Interface
    • GMII Transmit
    • GMII Receive
    • RGMII Transmit
    • RGMII Receive
    • MII Transmit
    • MII Receive
    • IEEE 1588v2 Timestamp
• 8. Design Considerations
  • Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA
    • MAC and PCS With GX Transceivers
    • MAC and PCS With LVDS Soft-CDR I/O
  • Sharing PLLs in Devices with LVDS Soft-CDR I/O
  • Sharing PLLs in Devices with GIGE PHY
  • Sharing Transceiver Quads
  • Migrating From Old to New User Interface For Existing Designs
    • Exposed Ports in the New User Interface
• 9. Timing Constraints
  • Creating Clock Constraints
  • Recommended Clock Frequency
• 10. Testbench
  • Triple-Speed Ethernet Testbench Architecture
  • Testbench Components
  • Testbench Verification
  • Testbench Configuration
  • Test Flow
  • Simulation Model
    • Generate the Simulation Model
    • Simulate the IP Core
    • Simulation Model Files
• 11. Software Programming Interface
  • Driver Architecture
  • Directory Structure
  • PHY Definition
  • Using Multiple SG-DMA Descriptors
  • Using Jumbo Frames
  • API Functions
    • alt_tse_mac_get_common_speed()
    • alt_tse_mac_set_common_speed()
    • alt_tse_phy_add_profile()
    • alt_tse_system_add_sys()
    • triple_speed_ethernet_init()
    • tse_mac_close()
    • tse_mac_raw_send()
    • tse_mac_setGMII mode()
    • tse_mac_setMIImode()
    • tse_mac_SwReset()
  • Constants
• A. Ethernet Frame Format
  • Basic Frame Format
  • VLAN and Stacked VLAN Frame Format
  • Pause Frame Format
    • Pause Frame Generation
• B. Simulation Parameters
  • Functionality Configuration Parameters
  • Test Configuration Parameters
• C. Time-of-Day (ToD) Clock
  • ToD Clock Features
  • ToD Clock Device Family Support
  • ToD Clock Performance and Resource Utilization
  • ToD Clock Parameter Setting
  • ToD Clock Interface Signals
    • ToD Clock Avalon-MM Control Interface Signals
    • ToD Clock Avalon-ST Transmit Interface Signals
  • ToD Clock Configuration Register Space
    • Adjusting ToD Clock Drift
• D. ToD Synchronizer
  • ToD Synchronizer Block
  • ToD Synchronizer Parameter Settings
  • ToD Synchronizer Signals
    • ToD Synchronizer Common Clock and Reset Signals
    • ToD Synchronizer Interface Signals
• E. Packet Classifier
  • Packet Classifier Block
  • Packet Classifier Signals
    • Packet Classifier Common Clock and Reset Signals
    • Packet Classifier Avalon-ST Interface Signals
    • Packet Classifier Ingress Control Signals
    • Packet Classifier Control Insert Signals
    • Packet Classifier Timestamp Field Location Signals
• F. Additional Information
  • Document Revision History
  • How to Contact Altera