Document Outline

• List of Figures
• List of Tables
• Overview
  • 1.1 General Description
  • 1.2 Features
• Architecture Overview
  • 2.1 GX1 Module
    • 2.1.1 Memory Controller
    • 2.1.2 Fast-PCI Bus
    • 2.1.3 Display
  • 2.2 Video Processor Module
    • 2.2.1 GX1 Module Interface
    • 2.2.2 Video Input Port
    • 2.2.3 Core Logic Module Interface
    • 2.2.4 CRT DAC
  • 2.3 Core Logic Module
    • 2.3.1 Other Core Logic Module Interfaces
  • 2.4 SuperI/O Module
  • 2.5 Clock, Timers, and Reset Logic
    • 2.5.1 Reset Logic
      • 2.5.1.1 Power-On Reset
      • 2.5.1.2 System Reset
• Signal Definitions
  • 3.1 Ball Assignments
  • 3.2 Strap Options
  • 3.3 Multiplexing Configuration
  • 3.4 Signal Descriptions
    • 3.4.1 System Interface
    • 3.4.2 Memory Interface Signals
    • 3.4.3 Video Port Interface Signals
    • 3.4.4 CRT/TFT Interface Signals
    • 3.4.5 TV Interface Signals
    • 3.4.6 ACCESS.bus Interface Signals
    • 3.4.7 PCI Bus Interface Signals
    • 3.4.8 Sub-ISA Interface Signals
    • 3.4.9 Low Pin Count (LPC) Bus Interface Signals
    • 3.4.10 IDE Interface Signals
    • 3.4.11 Universal Serial Bus (USB) Interface Signals
    • 3.4.12 Serial Ports (UARTs) Interface Signals
    • 3.4.13 Parallel Port Interface Signals
    • 3.4.14 Fast Infrared (IR) Port Interface Signals
    • 3.4.15 AC97 Audio Interface Signals
    • 3.4.16 Power Management Interface Signals
    • 3.4.17 GPIO Interface Signals
    • 3.4.18 Debug Monitoring Interface Signals
    • 3.4.19 JTAG Interface Signals
    • 3.4.20 Test and Measurement Interface Signals
    • 3.4.21 Power and Ground Connections
• General Configuration Block
  • 4.1 Configuration Block Addresses
  • 4.2 Pin Multiplexing, Interrupt Selection, and Base Address Registers
  • 4.3 WATCHDOG
    • 4.3.1 Functional Description
      • 4.3.1.1 WATCHDOG Timer
    • 4.3.2 WATCHDOG Registers
      • 4.3.2.1 Usage Hints
  • 4.4 High-Resolution Timer
    • 4.4.1 Functional Description
    • 4.4.2 High-Resolution Timer Registers
      • 4.4.2.1 Usage Hints
  • 4.5 Clock Generators and PLLs
    • 4.5.1 27 MHz Crystal Oscillator
    • 4.5.2 GX1 Module Core Clock
    • 4.5.3 Internal Fast-PCI Clock
    • 4.5.4 SuperI/O Clocks
    • 4.5.5 Core Logic Module Clocks
    • 4.5.6 Video Processor Clocks
    • 4.5.7 Clock Registers
• SuperI/O Module
  • 5.1 Features
  • 5.2 Module Architecture
  • 5.3 Configuration Structure / Access
    • 5.3.1 Index-Data Register Pair
    • 5.3.2 Banked Logical Device Registers
    • 5.3.3 Default Configuration Setup
    • 5.3.4 Address Decoding
  • 5.4 Standard Configuration Registers
    • 5.4.1 SIO Control and Configuration Registers
    • 5.4.2 Logical Device Control and Configuration
      • 5.4.2.1 LDN 00h - Real-Time Clock
      • 5.4.2.2 LDN 01h - System Wakeup Control
      • 5.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3
      • 5.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2
      • 5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2
      • 5.4.2.6 LDN 07h - Parallel Port
  • 5.5 Real-Time Clock (RTC)
    • 5.5.1 Bus Interface
    • 5.5.2 RTC Clock Generation
      • 5.5.2.1 Internal Oscillator
      • 5.5.2.2 External Oscillator
      • 5.5.2.3 Timing Generation
      • 5.5.2.4 Timekeeping
      • 5.5.2.5 Alarms
      • 5.5.2.6 Power Supply
      • 5.5.2.7 System Power States
      • 5.5.2.8 Oscillator Activity
      • 5.5.2.9 Interrupt Handling
      • 5.5.2.10 Battery-Backed RAMs and Registers
    • 5.5.3 RTC Registers
      • 5.5.3.1 Usage Hints
    • 5.5.4 RTC General-Purpose RAM Map
  • 5.6 System Wakeup Control (SWC)
    • 5.6.1 Event Detection
      • 5.6.1.1 Audio Codec Event
      • 5.6.1.2 CEIR Address
    • 5.6.2 SWC Registers
  • 5.7 ACCESS.bus Interface
    • 5.7.1 Data Transactions
    • 5.7.2 Start and Stop Conditions
    • 5.7.3 Acknowledge (ACK) Cycle
    • 5.7.4 Acknowledge After Every Byte Rule
    • 5.7.5 Addressing Transfer Formats
    • 5.7.6 Arbitration on the Bus
    • 5.7.7 Master Mode
      • 5.7.7.1 Master Stop
    • 5.7.8 Slave Mode
    • 5.7.9 Configuration
    • 5.7.10 ACB Registers
  • 5.8 Legacy Functional Blocks
    • 5.8.1 Parallel Port
      • 5.8.1.1 Parallel Port Register and Bit Maps
    • 5.8.2 UART Functionality (SP1 and SP2)
      • 5.8.2.1 UART Mode Register Bank Overview
      • 5.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality
    • 5.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality
      • 5.8.3.1 IR/SP3 Mode Register Bank Overview
      • 5.8.3.2 IRCP/SP3 Register and Bit Maps
• Core Logic Module
  • 6.1 Feature List
  • 6.2 Module Architecture
    • 6.2.1 Fast-PCI Interface to External PCI Bus
      • 6.2.1.1 Processor Mastered Cycles
      • 6.2.1.2 External PCI Mastered Cycles
      • 6.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles
      • 6.2.1.4 External PCI Bus
      • 6.2.1.5 Bus Master Request Priority
    • 6.2.2 PSERIAL Interface
      • 6.2.2.1 Video Retrace Interrupt
    • 6.2.3 IDE Controller
      • 6.2.3.1 IDE Configuration Registers
      • 6.2.3.2 PIO Mode
      • 6.2.3.3 Bus Master Mode
      • 6.2.3.4 UltraDMA/33 Mode
    • 6.2.4 Universal Serial Bus
    • 6.2.5 Sub-ISA Bus Interface
      • 6.2.5.1 Sub-ISA Bus Cycles
      • 6.2.5.2 Sub-ISA Support of Delayed PCI Transactions
      • 6.2.5.3 Sub-ISA Bus Data Steering
      • 6.2.5.4 I/O Recovery Delays
      • 6.2.5.5 ISA DMA
      • 6.2.5.6 ROM Interface
      • 6.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing
    • 6.2.6 AT Compatibility Logic
      • 6.2.6.1 DMA Controller
      • 6.2.6.2 Programmable Interval Timer
      • 6.2.6.3 Programmable Interrupt Controller
    • 6.2.7 I/O Ports 092h and 061h System Control
      • 6.2.7.1 I/O Port 092h System Control
      • 6.2.7.2 I/O Port 061h System Control
      • 6.2.7.3 SMI Generation for NMI
    • 6.2.8 Keyboard Support
      • 6.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset
    • 6.2.9 Power Management Logic
      • 6.2.9.1 CPU States
      • 6.2.9.2 Sleep States
      • 6.2.9.3 Power Planes Control
      • 6.2.9.4 Power Management Events
      • 6.2.9.5 Usage Hints
    • 6.2.10 Power Management Programming
      • 6.2.10.1 APM Support
      • 6.2.10.2 CPU Power Management
      • 6.2.10.3 Peripheral Power Management
      • 6.2.10.4 Power Management Programming Summary
    • 6.2.11 GPIO Interface
    • 6.2.12 Integrated Audio
      • 6.2.12.1 Data Transport Hardware
      • 6.2.12.2 AC97 Codec Interface
      • 6.2.12.3 VSA Technology Support Hardware
      • 6.2.12.4 IRQ Configuration Registers
      • 6.2.12.5 LPC Interface
      • 6.2.12.6 LPC Interface Signal Definitions
      • 6.2.12.7 Cycle Types
      • 6.2.12.8 LPC Interface Support
  • 6.3 Register Descriptions
    • 6.3.1 PCI Configuration Space and Access Methods
    • 6.3.2 Register Summary
  • 6.4 Chipset Register Space
    • 6.4.1 Bridge, GPIO, and LPC Registers - Function 0
      • 6.4.1.1 GPIO Support Registers
      • 6.4.1.2 LPC Support Registers
    • 6.4.2 SMI Status and ACPI Registers - Function 1
      • 6.4.2.1 SMI Status Support Registers
      • 6.4.2.2 ACPI Support Registers
    • 6.4.3 IDE Controller Registers - Function 2
      • 6.4.3.1 IDE Controller Support Registers
    • 6.4.4 Audio Registers - Function 3
      • 6.4.4.1 Audio Support Registers
    • 6.4.5 X-Bus Expansion Interface - Function 5
      • 6.4.5.1 X-Bus Expansion Support Registers
    • 6.4.6 USB Controller Registers - PCIUSB
    • 6.4.7 ISA Legacy Register Space
• Video Processor Module
  • 7.1 Module Architecture
  • 7.2 Functional Description
    • 7.2.1 Video Input Port (VIP)
      • 7.2.1.1 Direct Video Mode
      • 7.2.1.2 Direct VBI Mode
      • 7.2.1.3 Capture Video Mode
      • 7.2.1.4 Capture VBI Mode
    • 7.2.2 Video Block
      • 7.2.2.1 Video Input Formatter
      • 7.2.2.2 Horizontal Downscaler with 4-Tap Filtering
      • 7.2.2.3 Line Buffers
      • 7.2.2.4 Formatter
      • 7.2.2.5 2-Tap Vertical and Horizontal Upscalers
    • 7.2.3 Mixer/Blender Block
      • 7.2.3.1 YUV to RGB CSC in Video Data Path
      • 7.2.3.2 Gamma Correction
      • 7.2.3.3 RGB to YUV CSC
      • 7.2.3.4 1/2 Y Flicker Filter
      • 7.2.3.5 Color/Chroma Key
      • 7.2.3.6 Color/Chroma Key and Mixer/Blender
    • 7.2.4 TVOUT Block
      • 7.2.4.1 Flicker Filter and Scan Rate Conversion
      • 7.2.4.2 Pre-Encoder Horizontal Scaler
      • 7.2.4.3 Video Output Port (VOP)
      • 7.2.4.4 TV Encoder Timing Generator
      • 7.2.4.5 TV Encoder
    • 7.2.5 VESA DDSC2B and DPMS Support
    • 7.2.6 Integrated DACs
    • 7.2.7 TFT Interface
    • 7.2.8 Integrated PLL
  • 7.3 Register Descriptions
    • 7.3.1 Register Summary
    • 7.3.2 Video Processor Registers - Function 4
      • 7.3.2.1 Video Processor Support Registers - F4BAR0
      • 7.3.2.2 VIP Support Registers - F4BAR2
• Debugging and Monitoring
  • 8.1 Testability (JTAG)
    • 8.1.1 Mandatory Instruction Support
    • 8.1.2 Optional Instruction Support
    • 8.1.3 JTAG Chain
• Electrical Specifications
  • 9.1 General Specifications
    • 9.1.1 Electro Static Discharge (ESD)
    • 9.1.2 Power/Ground Connections and Decoupling
    • 9.1.3 Absolute Maximum Ratings
    • 9.1.4 Operating Conditions
    • 9.1.5 DC Current
      • 9.1.5.1 Power State Parameter Definitions
      • 9.1.5.2 Definition and Measurement Techniques of Current Parameters
      • 9.1.5.3 Definition of System Conditions for Measuring On Parameters
      • 9.1.5.4 DC Current Measurements
    • 9.1.6 Ball Capacitance and Inductance
    • 9.1.7 Pull-Up and Pull-Down Resistors
  • 9.2 DC Characteristics
    • 9.2.1 INAB DC Characteristics
    • 9.2.2 INBTN DC Characteristics
    • 9.2.3 INPCI DC Characteristics
    • 9.2.4 INSTRP DC Characteristics
    • 9.2.5 INT DC Characteristics
    • 9.2.6 INTS DC Characteristics
    • 9.2.7 INTS1 DC Characteristics
    • 9.2.8 INUSB DC Characteristics
    • 9.2.9 OAC97 DC Characteristics
    • 9.2.10 ODn DC Characteristics
    • 9.2.11 ODPCI DC Characteristics
    • 9.2.12 Op/n DC Characteristics
    • 9.2.13 OPCI DC Characteristics
    • 9.2.14 OUSB DC Characteristics
    • 9.2.15 TSp/n DC Characteristics
      • 9.2.15.1 Exceptions
  • 9.3 AC Characteristics
    • 9.3.1 Memory Controller Interface
    • 9.3.2 Video Port (VP) Interface
    • 9.3.3 CRT and TFT Interface
    • 9.3.4 TV Interface
    • 9.3.5 ACCESS.bus Interface
    • 9.3.6 PCI Bus
      • 9.3.6.1 Measurement and Test Conditions
    • 9.3.7 Sub-ISA Interface
    • 9.3.8 LPC Interface
    • 9.3.9 IDE Interface Timing
    • 9.3.10 Universal Serial Bus (USB)
    • 9.3.11 Serial Port (UART)
    • 9.3.12 Fast IR Port Timing
    • 9.3.13 Parallel Port Timing
      • 9.3.13.1 Extended Capabilities Port (ECP) Timing
    • 9.3.14 Audio Interface Timing (AC97)
    • 9.3.15 Power Management
    • 9.3.16 Power-Up Sequencing
    • 9.3.17 JTAG Interface
• Package Specifications
  • 10.1 Thermal Characteristics
    • 10.1.1 Heatsink Considerations
  • 10.2 Physical Dimensions
• Support Documentation
  • A.1 Order Information
  • A.2 Macrovision Product Notice
  • A.3 Data Book Revision History