Document Outline

• FEATURES
• GENERAL DESCRIPTION
• SPECIFICATIONS
• ABSOLUTE MAXIMUM RATINGS
• ORDERING GUIDE
• PIN FUNCTION DESCRIPTIONS
• TERMINOLOGY
• ADC SPECIFICATIONS
  • Integral Nonlinearity
  • Differential Nonlinearity
  • Offset Error
  • Full-Scale Error
  • Signal to (Noise + Distortion) Ratio
  • Total Harmonic Distortion
• DAC SPECIFICATIONS
  • Relative Accuracy
  • Voltage Output Settling Time
  • Digital-To-Analog Glitch Impulse
• ARCHITECTURE, MAIN FEATURES
• MEMORY ORGANIZATION
• OVERVIEW OF MCU-RELATED SFRs
  • Accumulator SFR
  • B SFR
  • Stack Pointer SFR
  • Data Pointer
  • Program Status Word SFR
  • Power Control SFR
• SPECIAL FUNCTION REGISTERS
• ADC CIRCUIT INFORMATION
  • General Overview
  • ADC Transfer Function
  • Typical Operation
  • ADCCON1 — (ADC Control SFR #1)
  • ADCCON2 — (ADC Control SFR #2)
  • ADCCON3 — (ADC Control SFR #3)
  • Driving the A/D Converter
  • Voltage Reference Connections
  • Configuring the ADC
  • ADC DMA Mode
  • Micro Operation During the ADC DMA Mode
  • The Offset and Gain Calibration Coefficients
  • Calibration
• NONVOLATILE FLASH MEMORY
  • Flash Memory Overview
  • Flash/EE Memory and the ADuC812
  • ADuC812 Flash/EE Memory Reliability
  • Using the Flash/EE Program Memory
    • Serial Downloading (In-Circuit Programming)
    • Parallel Programming
  • Using the Flash/EE Data Memory
  • ECON–Flash/EE Memory Control SFR
  • Flash/EE Memory Timing
  • Using the Flash/EE Memory Interface
  • Erase-All
  • Program a Byte
• USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS
  • Using the D/A Converter
• WATCHDOG TIMER
• POWER SUPPLY MONITOR
• SERIAL PERIPHERAL INTERFACE
  • MISO (Master In, Slave Out Data I/O Pin), Pin #19
  • MOSI (Master Out, Slave In Pin), Pin #27
  • SCLOCK (Serial Clock I/O Pin), Pin #26
  • SS (Slave Select Input Pin), Pin #12
  • Using the SPI Interface
  • SPI Interface — Master Mode
  • SPI Interface — Slave Mode
• I2C COMPATIBLE INTERFACE
• 8051-COMPATIBLE ON-CHIP PERIPHERALS
  • Parallel I/O Ports 0–3
  • Timers/Counters
  • Timer/Counter 0 and 1 Data Registers
  • TH0 and TL0
  • TH1 and TL1
• TIMER/COUNTER 0 AND 1 OPERATING MODES
  • Mode 0 (13-Bit Timer/Counter)
  • Mode 1 (16-Bit Timer/Counter)
  • Mode 2 (8-Bit Timer/Counter with Auto Reload)
  • Mode 3 (Two 8-Bit Timer/Counters)
  • Timer/Counter 2 Data Registers
  • TH2 and TL2
  • RCAP2H and RCAP2L
  • Timer/Counter Operation Modes
  • 16-Bit Autoreload Mode
  • 16-Bit Capture Mode
• UART SERIAL INTERFACE
  • Mode 0: 8-Bit Shift Register Mode
  • Mode 1: 8-Bit UART, Variable Baud Rate
  • Mode 2: 9-Bit UART with Fixed Baud Rate
  • Mode 3: 9-Bit UART with Variable Baud Rate
  • UART Serial Port Baud Rate Generation
  • Timer 1 Generated Baud Rates
  • Timer 2 Generated Baud Rates
• INTERRUPT SYSTEM
  • Interrupt Priority
  • Interrupt Vectors
• ADuC812 HARDWARE DESIGN CONSIDERATIONS
  • Clock Oscillator
  • External Memory Interface
  • Power-On Reset Operation
  • Power Supplies
  • Power Consumption
  • Power-Saving Modes
  • Grounding and Board Layout Recommendations
• OTHER HARDWARE CONSIDERATIONS
  • In-Circuit Serial Download Access
  • Embedded Serial Port Debugger
  • Single-Pin Emulation Mode
  • Enhanced-Hooks Emulation Mode
  • Typical System Configuration
• QUICKSTART DEVELOPMENT SYSTEM
  • Download – In-Circuit Serial Downloader
  • DeBug – In-Circuit Debugger
  • ADSIM – Windows Simulator
• TIMING SPECIFICATIONS
• OUTLINE DIMENSIONS
• Revision History