Document Outline

• ARTM-831X
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Introduction
  • 1.1 Overview
  • 1.2 Features
    • 1.2.1 ARTM 8310_base
    • 1.2.2 ARTM-831X_E1/T1
    • 1.2.3 ARTM-831X_DS3/OC3
  • 1.3 Standard Compliances
  • 1.4 Mechanical Data
  • 1.5 Ordering Information
  • 1.6 Product Identification
• Hardware Preparation and Installation
  • 2.1 Unpacking and Inspecting the Module
  • 2.2 Environmental and Power Requirements
    • 2.2.1 Environmental Requirements
    • 2.2.2 RTM Power Specification
  • 2.3 Installing and Removing the RTM
    • 2.3.1 Installing the RTM
    • 2.3.2 Removing the RTM
  • 2.4 Installing and Removing SFP Modules
    • 2.4.1 Installing an SFP Module
    • 2.4.2 Removing an SFP Module
• Controls, LEDs, and Connectors
  • 3.1 Mechanical Layout
  • 3.2 Face Plate
    • 3.2.1 LEDs and Interfaces
    • 3.2.2 Connectors
      • 3.2.2.1 Faceplate Connectors
• Functional Description
  • 4.1 Block Diagram
  • 4.2 ARTM-831X Base Unit
    • 4.2.1 FPGA_base
      • 4.2.1.1 SPI Interface
      • 4.2.1.2 Ref Clock Selection
      • 4.2.1.3 Register Description
    • 4.2.2 QUAD 1Gb Ethernet Interfaces
      • 4.2.2.1 Transceiver
      • 4.2.2.2 Ethernet LED's
      • 4.2.2.3 Management Interface
    • 4.2.3 10G Ethernet Interface
      • 4.2.3.1 Transceiver
      • 4.2.3.2 Management Interface
    • 4.2.4 Synchronous Clock Functionality
    • 4.2.5 BITS Interfaces
    • 4.2.6 OC3 option
      • 4.2.6.1 SFP Overhead Signals
      • 4.2.6.2 ESSI Signals
    • 4.2.7 On Board Resources (IPMI)
      • 4.2.7.1 Temperature Sensors
      • 4.2.7.2 FRU Data and Mezzanine Presence Detect
  • 4.3 E1/T1 Mezzanine Expansion Unit
    • 4.3.1 TSI FPGA
      • 4.3.1.1 SPI Interface
      • 4.3.1.2 Clock Selection
      • 4.3.1.3 Local Bus
      • 4.3.1.4 TSIP2SERDES Interface
      • 4.3.1.5 Register Description
    • 4.3.2 TSI-Extender FPGA
      • 4.3.2.1 SPI Interface
      • 4.3.2.2 Clock selection
      • 4.3.2.3 Register Description
    • 4.3.3 E1/T1 Framer-LIU
      • 4.3.3.1 H-MVIP Interface
      • 4.3.3.2 Local Bus
      • 4.3.3.3 Line interface & redundancy support
      • 4.3.3.4 Locate and Type Detect Function (patch panel)
      • 4.3.3.5 ESF Sync 166Hz Routing
    • 4.3.4 FRU Data
  • 4.4 DS3/OC3 Mezzanine Expansion Unit
    • 4.4.1 TSI FPGA
      • 4.4.1.1 SPI Interface
      • 4.4.1.2 Clock selection
      • 4.4.1.3 PCIexpress x1 Interface
      • 4.4.1.4 Local Bus
      • 4.4.1.5 TSIP2 SERDES Interface
      • 4.4.1.6 Register Description
    • 4.4.2 TSI-Extender FPGA
      • 4.4.2.1 SPI Interface
      • 4.4.2.2 Clock selection
      • 4.4.2.3 Status/Control & Alarm Signals
      • 4.4.2.4 Register Description
    • 4.4.3 PM8310 TEMUX336 SDH/Sonet Framer
      • 4.4.3.1 SBI336 Interface
      • 4.4.3.2 Local Bus
      • 4.4.3.3 Line Side Interfaces
      • 4.4.3.4 ESSI Interface and Routing
    • 4.4.4 E1/T1 Framer-LIU
      • 4.4.4.1 H-MVIP Interface
      • 4.4.4.2 Local Bus
    • 4.4.5 Line Interface and Redundancy Support
      • 4.4.5.1 Locate and type detect function (patch panel)
    • 4.4.6 FRU data
• Module Management Controller
  • 5.1 Functional Overview
  • 5.2 Firmware architecture
  • 5.3 HPM.1 Firmware Upgrade and Crisis Recovery
  • 5.4 Accessing SFP EEPROMs
  • 5.5 Artesyn OEM Command Set
  • 5.6 Patch Panel Detection
  • 5.7 IPMI Hardware Watchdog
  • 5.8 SFP I2C Selection
• FRU Information and SDR Summary
  • 6.1 FRU Information
  • 6.2 Power Configuration
  • 6.3 Sensor Data Records
    • 6.3.1 SFP Device Inserted Sensors
    • 6.3.2 SFP TXFAULT Sensors
    • 6.3.3 P(1-3) HA Status and P(1-3) Healthy Sensors
    • 6.3.4 Voltage and Temperature Sensors
• Sensor Data Records
  • 7.1 Sensor Data Records
• Base ARTM FPGA
  • 8.1 Base ARTM Architectural Overview
    • 8.1.1 Unit Description
  • 8.2 Signals
    • 8.2.1 Global Signals
    • 8.2.2 RTM SPI Interface (Slave)
    • 8.2.3 Mezzanine SPI Interface (Slave)
    • 8.2.4 Mezzanine TSI Telecom clocks
    • 8.2.5 MMC I2C Interface (Slave)
    • 8.2.6 I2C Interfaces to Sonet SFP and 10GE SFP+
    • 8.2.7 Telecom Base Clock Receive Clocks
    • 8.2.8 Telecom Clocks
    • 8.2.9 Status Sonet SFP
    • 8.2.10 Control Sonet SFP
    • 8.2.11 10GE Status/Control Signals
    • 8.2.12 GE Control Signals
    • 8.2.13 Ethernet Clock Signals
    • 8.2.14 BITS 1 Signals
    • 8.2.15 BITS 2 Signals
    • 8.2.16 Identification Signals
    • 8.2.17 Debug LEDs
    • 8.2.18 Spare Signals
    • 8.2.19 Configuration Signals
  • 8.3 Registers
    • 8.3.1 ARTM Base FPGA Register Overview
      • 8.3.1.1 ARTM Base FPGA Code Main-Version
      • 8.3.1.2 SFP I2C select Register
      • 8.3.1.3 ARTM Base FPGA Code Sub-Version
      • 8.3.1.4 SFP TXFAULT Status
      • 8.3.1.5 SFP MOD_ABS Status
      • 8.3.1.6 SFP TXDIS Control
      • 8.3.1.7 10 GE Status Register
      • 8.3.1.8 10 GE Control Register
      • 8.3.1.9 MMC Scratch Register
      • 8.3.1.10 RTM Scratch Register
      • 8.3.1.11 Telecom Reference Clock Selection
      • 8.3.1.12 GE Control Register
      • 8.3.1.13 Force CRC Error Register
      • 8.3.1.14 Test Register
      • 8.3.1.15 Other Status Signals
      • 8.3.1.16 SFP TXFAULT Level Changed
      • 8.3.1.17 SFP TXFAULT interrupt enable
      • 8.3.1.18 SFP MOD_ABS changed
      • 8.3.1.19 SFP MOD_ABS interrupt enable
      • 8.3.1.20 10 GE Status changed
      • 8.3.1.21 10 GE Status interrupt enable
      • 8.3.1.22 Telecom Reference Clock Divider Registers
      • 8.3.1.23 ARTM Interrupt Group Status
      • 8.3.1.24 Identification Register
      • 8.3.1.25 FPGA Code SPI Update Registers
      • 8.3.1.26 ARTM Telecom Clock Monitor Registers
      • 8.3.1.27 ARTM Ethernet Reset Control Register
  • 8.4 Reset Structure
  • 8.5 Clocking Scheme
  • 8.6 Logic Blocks
    • 8.6.1 RTM SPI Interface
    • 8.6.2 Mezzanine SPI Interface
    • 8.6.3 MMC I2C Slave Interface
      • 8.6.3.1 MMC I2C Slave Read Register
      • 8.6.3.2 MMC I2C Slave Write Register
      • 8.6.3.3 MMC I2C Forwarding
      • 8.6.3.4 MMC I2C SCL Stretching
    • 8.6.4 Shared Registers
    • 8.6.5 IP Only Registers
    • 8.6.6 TDM Only Registers
    • 8.6.7 Hardware Protection
    • 8.6.8 ARTM Base FPGA Configuration Supervision
    • 8.6.9 ARTM Base FPGA Dual Configuration
• TSI FPGA
  • 9.1 Architectural Overview
    • 9.1.1 Unit Description
  • 9.2 Device Specifics
    • 9.2.1 FPGA Device Type
  • 9.3 TSI FPGA Signals Overview
  • 9.4 Logic Blocks
    • 9.4.1 TSI - Time Slot Interchanger
    • 9.4.2 GR8
    • 9.4.3 Testpattern Generator (input)
    • 9.4.4 Testpattern Comparator (input)
    • 9.4.5 Testpattern Generator (output)
    • 9.4.6 Testpattern Generator (output)
    • 9.4.7 Frame Start Pulse Generator
    • 9.4.8 PCIexpress Interface
    • 9.4.9 Local Bus Master Interface
    • 9.4.10 SPI Control Interface in Master Mode
    • 9.4.11 SPI Expander Interface
    • 9.4.12 Interrupt Controller
    • 9.4.13 Debug LEDs
  • 9.5 RTM FPGA HW/SW Interfaces
    • 9.5.1 RTM FPGA Address map Overview
    • 9.5.2 RTM FPGA Memories and Registers Detailed
      • 9.5.2.1 TSI Memory (TsiMem)
      • 9.5.2.2 GR8 Memory (Gr8Mem)
      • 9.5.2.3 SerDes Client Interface (SerDesClientIf)
      • 9.5.2.4 TSI Registers (TsiRegs)
      • 9.5.2.5 Gr8 Registers (Gr8Regs)
      • 9.5.2.6 TSI Interior/Exterior Test Pattern Generator Block (TsiTstPatGenBlk)
      • 9.5.2.7 TSI Interior/Exterior Test Pattern Comparator Block (TsiTstPatCmpBlk)
      • 9.5.2.8 Tsi to Serdes Converter Block (Tsi2SerBlk)
      • 9.5.2.9 Deserializer to TSI Allocater Block (Des2TsiBlk)
      • 9.5.2.10 Transport Overhead Registers (TohRegs)
      • 9.5.2.11 General Register (GnrlRegs)
      • 9.5.2.12 General Test Registers (GenTestRegs)
      • 9.5.2.13 Framer and Line Interface Unit Sideband Signal Registers (FrLiuSdBndRegs)
      • 9.5.2.14 Configuration Prom Update Registers accessed through RTM FPGA as bridge to SPI bus 0 (CfgPrmUpd)
      • 9.5.2.15 External components accessed through RTM FPGA as bridge to SPI bus 1 (ExtBridgedCompSpi1)
      • 9.5.2.16 External components accessed through RTM FPGA as bridge to SPI bus 2 (ExtBridgedCompSpi2)
      • 9.5.2.17 External components accessed through RTM FPGA as bridge to SPI bus 3 (ExtBridgedCompSpi3)
      • 9.5.2.18 External components accesses through RTM FPGA as bridge to local bus (ExtBridgedComp)
    • 9.5.3 PCI Configuration Space
      • 9.5.3.1 Overview
      • 9.5.3.2 Detailed Description
  • 9.6 TSI channel mapping
• EXT FPGA
  • 10.1 Ext FPGA Overview
  • 10.2 Device Specifics
    • 10.2.1 FPGA Device Type
  • 10.3 Logic Blocks
    • 10.3.1 SPI Interface
    • 10.3.2 Debug LEDs
  • 10.4 EXT FPGA HW/SW Interfaces
    • 10.4.1 EXT FPGA Addressmap Overview
    • 10.4.2 EXT FPGA Registers Detailed Description
      • 10.4.2.1 General Register (GnrlRegs)
      • 10.4.2.2 Configuration Prom Update Registers (CfgPrmUpd)
      • 10.4.2.3 General Test Registers (GenTestRegs)
      • 10.4.2.4 Framer and Line Interface Unit Sideband Signal Registers (FrLiuSdBndRegs)
• A Related Documentation
  • A.1 Artesyn Embedded Technologies - Embedded Computing Documentation
• Safety Notes
  • EMC
  • Installation
  • Operation
  • Environment
  • SFP Modules
• Sicherheitshinweise
  • EMV
  • Installation
  • Betrieb
  • Umweltschutz
  • SFP Modules