Document Outline

• iVPX7225
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Safety Notes
  • System Installation
  • Operation
  • Expansion and FRU Replacement
  • External Battery or Super Capacitor
  • Environment
• Sicherheitshinweise
  • System Installation
  • Betrieb
  • Erweiterung und FRU Austausch
  • Externe Batterie or Super-Kondensator
  • Environment
• Introduction
  • 1.1 Features
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
    • 1.3.1 Air Cooled
    • 1.3.2 Conduction Cooled
  • 1.4 Ordering Information
    • 1.4.1 Supported Board Models
  • 1.5 Product Identification
• Hardware Preparation and Installation
  • 2.1 Overview
  • 2.2 Unpacking and Inspecting the Board
  • 2.3 Environmental and Power Requirements
    • 2.3.1 Environmental Requirements
    • 2.3.2 Power Requirements
  • 2.4 Installing the Accessories
    • 2.4.1 Installing the XMC on Air Cooled Board
    • 2.4.2 Installing the XMC on Conduction Cooled Board
    • 2.4.3 Rear Transition Module
  • 2.5 Installing and Removing the Board
    • 2.5.1 Installing Air Cooled iVPX7225
    • 2.5.2 Installing Conduction Cooled iVPX7225
• Controls, LEDs and Connectors
  • 3.1 Board Layout
  • 3.2 Planar LEDs
    • 3.2.1 Debug LEDs
    • 3.2.2 POST Code LEDs
  • 3.3 Front Panel Connectors and LEDs
  • 3.4 Backplane Connectors
    • 3.4.1 P0 Connector
    • 3.4.2 P1 Connector
    • 3.4.3 P2 Connector
  • 3.5 XMC Connector
  • 3.6 Switches
• Functional Description
  • 4.1 Block Diagram
  • 4.2 Processor
  • 4.3 Chipset
  • 4.4 System Memory
  • 4.5 Ethernet Interfaces
  • 4.6 PCI Express
  • 4.7 SATA
  • 4.8 USB
  • 4.9 Serial COM
  • 4.10 Video
    • 4.10.1 Rear DisplayPort
    • 4.10.2 VGA
  • 4.11 GPIO
  • 4.12 SMBus
  • 4.13 Boot Flash
  • 4.14 NAND Flash
  • 4.15 FRAM
  • 4.16 Trusted Platform Module
  • 4.17 Real Time Clock
  • 4.18 Watchdog Timer
  • 4.19 XMC Support
  • 4.20 Boot Firmware
  • 4.21 Operating System
• BIOS
  • 5.1 Overview
  • 5.2 Processor Initialization
  • 5.3 Memory Initialization
    • 5.3.1 Serial Presence Detect (SPD)
    • 5.3.2 Memory Test
    • 5.3.3 ECC Support
    • 5.3.4 DDR3 Refresh Rate
  • 5.4 Reset
  • 5.5 PCIe Initialization
  • 5.6 I/O Device Configuration
  • 5.7 Boot Options
  • 5.8 I/O Redirection
  • 5.9 BIOS Setup Layout
    • 5.9.1 Main Menu
    • 5.9.2 Boot Features
    • 5.9.3 Advanced Menu
    • 5.9.4 Processor Configuration
    • 5.9.5 Processor Power Management
    • 5.9.6 HDD Configuration
    • 5.9.7 Memory Configuration
    • 5.9.8 System Agent (SA) Configuration
    • 5.9.9 Graphics Configuration
    • 5.9.10 IGD Configuration
    • 5.9.11 PEG Port Configuration
    • 5.9.12 South Bridge Configuration
    • 5.9.13 SB USB Configuration
    • 5.9.14 SB Security Configuration
    • 5.9.15 Network Configuration
    • 5.9.16 SIO Configuration
    • 5.9.17 ME Configuration
    • 5.9.18 Thermal Configuration
    • 5.9.19 Platform Thermal Configuration
    • 5.9.20 Intel® Rapid Start Technology
    • 5.9.21 iVPX7225 Menu
    • 5.9.22 Security Menu
    • 5.9.23 TPM Configuration
    • 5.9.24 Boot Menu
    • 5.9.25 Exit Menu
  • 5.10 BIOS POST Codes
  • 5.11 Memory POST Codes
• Maps and Registers
  • 6.1 Flash Map
  • 6.2 BIOS Memory Map
• FPGA Registers
  • 7.1 FPGA Registers
    • 7.1.1 Blade Revision Register - 0x00
    • 7.1.2 FPGA Major Revision Register - 0x01
    • 7.1.3 FPGA Minor Revision Register - 0x02
    • 7.1.4 FPGA Date Code Register - 0x04
    • 7.1.5 FPGA Month Code Register - 0x05
    • 7.1.6 FPGA Year Code Register 0x06
    • 7.1.7 FPGA Reset Cause Register - 0x08
    • 7.1.8 Watchdog Control Register - 0x09
    • 7.1.9 Watchdog Re-trigger Register - 0x0A
    • 7.1.10 Memory Write Protect Register - 0x0B
    • 7.1.11 Power Good Status 1 Register - 0x0C
    • 7.1.12 Power Good Status 2 Register - 0x0D
    • 7.1.13 System Status Register - 0x0E
    • 7.1.14 Misc 1 Control and Status Register - 0x10
    • 7.1.15 Misc 2 Control and Status Register - 0x11
    • 7.1.16 DIP Switch Status Register - 0x14
    • 7.1.17 Misc 3 Control and Status Register - 0x15
    • 7.1.18 Boot Control and Status 1 Register - 0x16
    • 7.1.19 Boot Control and Status 2 Register - 0x17
    • 7.1.20 PCIE Switch Control and Status 1 Register - 0x18
    • 7.1.21 PCIE Switch Control and Status 2 Register - 0x19
    • 7.1.22 CPU Package Temperature Reading Register - 0x1C
    • 7.1.23 IPMC Inlet Temperature Sensor Status Register - 0x1D
    • 7.1.24 IPMC Outlet Temperature Sensor Status Register - 0x1E
    • 7.1.25 FRAM Page Access Register - 0x20
    • 7.1.26 VPX System Register - 0x24
    • 7.1.27 POST Code Latch Register - 0x28
    • 7.1.28 BIOS Boot Status Register - 0x2C
  • 7.2 FPGA SIO
    • 7.2.1 Super IO Configuration Registers
      • 7.2.1.1 Entering the Configuration State
      • 7.2.1.2 Exiting the Configuration State
      • 7.2.1.3 Configuration Mode
      • 7.2.1.4 Super IO Configuration Registers
      • 7.2.1.5 Global Control Configuration Registers
      • 7.2.1.6 Logical Device Configuration Registers
  • 7.3 UART Register Overview
    • 7.3.1 UART Registers DLAB=0
      • 7.3.1.1 Received Buffer Register (RBR)
      • 7.3.1.2 Transmitter Holding Register (THR)
      • 7.3.1.3 Interrupt Enable Register (IER)
      • 7.3.1.4 Interrupt Identification Register (IIR)
      • 7.3.1.5 FIFO Control Register (FCR)
      • 7.3.1.6 Line Control Register (LCR)
      • 7.3.1.7 Modem Control Register (MCR)
      • 7.3.1.8 Line Status Register (LSR)
      • 7.3.1.9 Modem Status Register (MSR)
      • 7.3.1.10 Scratch Register (SCR)
      • 7.3.1.11 Programmable Baud Rate Generator
• A Related Documentation
  • A.1 Artesyn Embedded Technologies - Embedded Computing Documentation
  • A.2 Related Specifications