Document Outline

• MVME2502
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Safety Notes
• Sicherheitshinweise
• Introduction
  • 1.1 Overview
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
  • 1.4 Ordering Information
  • 1.5 Product Identification
• Hardware Preparation and Installation
  • 2.1 Overview
  • 2.2 Unpacking and Inspecting the Board
  • 2.3 Requirements
    • 2.3.1 Environmental Requirements
    • 2.3.2 Power Requirements
    • 2.3.3 Equipment Requirements
  • 2.4 Configuring the Board
  • 2.5 Installing Accessories
    • 2.5.1 Rear Transition Module
    • 2.5.2 PMC/XMC Support
    • 2.5.3 Installation of MVME2502-HDMNTKIT1/MVME2502- HDMNTKIT2
  • 2.6 Installing and Removing the Board
  • 2.7 Completing the Installation
• Controls, LEDs, and Connectors
  • 3.1 Board Layout
  • 3.2 Front Panel
    • 3.2.1 Reset Switch
  • 3.3 LEDs
    • 3.3.1 Front Panel LEDs
    • 3.3.2 On-board LEDs
  • 3.4 Connectors
    • 3.4.1 Front Panel Connectors
      • 3.4.1.1 RJ45 with Integrated Magnetics (J1)
      • 3.4.1.2 Front Panel Serial Port (J4)
      • 3.4.1.3 USB Connector (J5)
      • 3.4.1.4 VMEBus P1 Connector
      • 3.4.1.5 VMEBus P2 Connector
    • 3.4.2 On-board Connectors
      • 3.4.2.1 SATA Connector (J3)
      • 3.4.2.2 PMC Connectors
      • 3.4.2.3 JTAG Connector (P6)
      • 3.4.2.4 COP Connector P50(15)
      • 3.4.2.5 XMC Connector (XJ1)
      • 3.4.2.6 XMC Connector (XJ2)
      • 3.4.2.7 Miscellaneous P2020 Debug Connectors(P4)
  • 3.5 Switches
    • 3.5.1 Geographical Address Switch (S1)
    • 3.5.2 SMT Configuration Switch (S2)
• Functional Description
  • 4.1 Block Diagram
  • 4.2 Chipset
    • 4.2.1 e500 Processor Core
    • 4.2.2 Integrated Memory Controller
    • 4.2.3 PCI Express Interface
    • 4.2.4 Local Bus Controller (LBC)
    • 4.2.5 Secure Digital Host Controller (SDHC)
    • 4.2.6 I2C Interface
    • 4.2.7 USB Interface
    • 4.2.8 DUART
    • 4.2.9 DMA Controller
    • 4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)
    • 4.2.11 General Purpose I/O (GPIO)
    • 4.2.12 Security Engine (SEC) 3.1
    • 4.2.13 Common On-Chip Processor (COP)
    • 4.2.14 P2020 Strapping Pins
  • 4.3 System Memory
  • 4.4 Timers
    • 4.4.1 Real Time Clock
    • 4.4.2 P2020 Internal Timer
    • 4.4.3 Watchdog Timer
    • 4.4.4 CPLD Tick Timer
  • 4.5 Ethernet Interfaces
  • 4.6 SPI Bus Interface
    • 4.6.1 SPI Flash Memory
    • 4.6.2 SPI Flash Programming
    • 4.6.3 Firmware Redundancy
    • 4.6.4 Crisis Recovery
  • 4.7 Front UART Control
  • 4.8 Rear UART Control
  • 4.9 PMC/XMC Sites
    • 4.9.1 PMC Add-on Card
    • 4.9.2 XMC Add-on Card
  • 4.10 SATA Interface
  • 4.11 VME Support
    • 4.11.1 Tsi148 VME Controller
  • 4.12 USB
  • 4.13 I2C Devices
  • 4.14 Reset/Control CPLD
  • 4.15 Power Management
    • 4.15.1 On-board Voltage Supply Requirement
    • 4.15.2 Power Up Sequencing Requirements
  • 4.16 Clock Structure
  • 4.17 Reset Structure
    • 4.17.1 Reset Sequence
  • 4.18 Thermal Management
  • 4.19 Real-Time Clock Battery
  • 4.20 Debugging Support
    • 4.20.1 POST Code Indicator
    • 4.20.2 JTAG Chain and Board
    • 4.20.3 Custom Debugging
  • 4.21 Rear Transition Module (RTM)
• Memory Maps and Registers
  • 5.1 Overview
  • 5.2 Memory Map
  • 5.3 Flash Memory Map
  • 5.4 Linux Devices Memory Map
  • 5.5 Programmable Logic Device (PLD) Registers
    • 5.5.1 PLD Revision Register
    • 5.5.2 PLD Year Register
    • 5.5.3 PLD Month Register
    • 5.5.4 PLD Day Register
    • 5.5.5 PLD Sequence Register
    • 5.5.6 PLD Power Good Monitor Register
    • 5.5.7 PLD LED Control Register
    • 5.5.8 PLD PCI/PMC/XMC (Slot1) Monitor Register
    • 5.5.9 PLD PCI/PMC/XMC (Slot2) Monitor Register
    • 5.5.10 PLD U-Boot and TSI Monitor Register
    • 5.5.11 PLD Boot Bank Register
    • 5.5.12 PLD Write Protect and I2C Debug Register
    • 5.5.13 PLD Test Register 1
    • 5.5.14 PLD Test Register 2
    • 5.5.15 PLD GPIO2 Interrupt Register
    • 5.5.16 PLD Shutdown and Reset Control and Reset Reason Register
    • 5.5.17 EMMC Reset Register
    • 5.5.18 PLD Watchdog Timer Refresh Register
    • 5.5.19 PLD Watchdog Control Register
    • 5.5.20 PLD Watchdog Timer Count Register
    • 5.5.21 PLD Watchdog Timer Count Value Register
  • 5.6 External Timer Registers
    • 5.6.1 Prescaler Register
    • 5.6.2 Control Registers
    • 5.6.3 Compare High and Low Word Registers
    • 5.6.4 Counter High and Low Word Registers
• Boot System
  • 6.1 Overview
  • 6.2 Accessing U-Boot
  • 6.3 Boot Options
    • 6.3.1 Booting from a Network
    • 6.3.2 Booting from an Optional SATA Drive
    • 6.3.3 Booting from a USB Drive
    • 6.3.4 Booting from an SD Card
    • 6.3.5 Booting VxWorks Through the Network
  • 6.4 Using the Persistent Memory Feature
  • 6.5 MVME2502 Specific U-Boot Commands
  • 6.6 Updating U-Boot
• Programming Model
  • 7.1 Overview
  • 7.2 Reset Configuration
  • 7.3 Interrupt Controller
  • 7.4 I2C Bus Device Addressing
  • 7.5 Ethernet PHY Address
  • 7.6 Other Software Considerations
    • 7.6.1 MRAM
    • 7.6.2 Real Time Clock
    • 7.6.3 Quad UART
    • 7.6.4 LBC Timing Parameters
  • 7.7 Clock Distribution
    • 7.7.1 System Clock
    • 7.7.2 Real Time Clock Input
    • 7.7.3 Local Bus Controller Clock Divisor
• A Replacing the Battery
  • A.1 Replacing the Battery
• B Related Documentation
  • B.1 Artesyn Embedded Technologies - Embedded Computing Documentation
  • B.2 Manufacturers’ Documents
  • B.3 Related Specifications