Document Outline

• LSI53C320 Ultra320 SCSI Bus Expander
  • Preface
  • Contents
  • Chapter1 Introduction
    • 1.1 General Description
      • Figure1.1 LSI53C320 SCSI Bus Modes
      • Table 1.1 Types of Operation
    • 1.2 Applications
      • Figure1.2 LSI53C320 Server Clustering
      • Table 1.2 SCSI Bus Length Limits in a Clustering Configuration
      • Figure1.3 LSI53C320 SCSI Bus Device
      • Table 1.3 SCSI Bus Length Limits
    • 1.3 Benefits of Ultra320 SCSI
    • 1.4 Benefits of SureLINK™ (Ultra320 SCSI Domain Validation)
    • 1.5 Benefits of LVDlink™ Technology
    • 1.6 Benefits of TolerANT® Technology
    • 1.7 Features
  • Chapter2 Functional Descriptions
    • 2.1 LSI53C320 Block Diagram Description
      • Figure2.1 LSI53C320 Block Diagram
      • 2.1.1 SCSI Control Blocks
      • 2.1.2 Retiming Logic Block
      • 2.1.3 Precision Delay Control Block
      • 2.1.4 State Machine Control Block
      • 2.1.5 DIFFSENS Receiver Block
    • 2.2 Ultra320 SCSI Functional Description
      • 2.2.1 Ultra320 SCSI Features
        • 2.2.1.1 Double Transition (DT) Clocking
        • 2.2.1.2 Intersymbol Interference (ISI) Compensation
          • Figure2.2 Paced Transfer Example
          • Figure2.3 Example of Precompensation
        • 2.2.1.3 Packetized Transfers
        • 2.2.1.4 Skew Compensation
        • 2.2.1.5 Cyclic Redundancy Check (CRC)
        • 2.2.1.6 LSI53C320 Requirements for Synchronous SCSI Negotiation
      • 2.2.2 SCSI Bus Interface
        • 2.2.2.1 SCSI Bus Modes
          • Table 2.1 DIFFSENS Voltage Levels
        • 2.2.2.2 SCSI Termination
      • 2.2.3 Maximum Cable Lengths
        • 2.2.3.1 Maximum Electrical Cable Length
          • Figure2.4 Electrical Cable Lengths at Ultra320 SCSI Speeds
        • 2.2.3.2 Maximum Physical Cable Length
          • Table 2.2 Total Cable Length for Ultra320 SCSI Using the LSI53C320
    • 2.3 SCSI Signal Processing
      • 2.3.1 Data and Data Parity Signals
      • 2.3.2 Select Signal
      • 2.3.3 Busy Signal
      • 2.3.4 Reset Signal
      • 2.3.5 Request and Acknowledge Signals
      • 2.3.6 Control/Data, Input/Output, Message, and Attention Signals
    • 2.4 Internal Control Descriptions
      • 2.4.1 Self-Calibration
      • 2.4.2 Delay Line Structures
        • 2.4.2.1 Data Path
        • 2.4.2.2 REQ/ACK Retiming
      • 2.4.3 Busy Filters
    • 2.5 Serial EEPROM Connection
      • Figure2.5 Serial EEPROM Connection
  • Chapter3 Signal Description
    • 3.1 Signal Grouping
      • Figure3.1 LSI53C320 Functional Signal Grouping
    • 3.2 SCSI Interface Signals
      • Table 3.1 SCSI A Side Interface Signals
      • Table 3.2 SCSI B Side Interface Signals
    • 3.3 Interface Control Signals
      • Table 3.3 Chip Interface Control Signals
    • 3.4 Serial EEPROM Signals
      • Table 3.4 Serial EEPROM Signals
    • 3.5 Power and Ground Signals
      • Table 3.5 Power and Ground Pins (Cont.)
    • 3.6 Test Signals
      • Table 3.6 Test Signals for LSI Logic Only
    • 3.7 Signal Layout Considerations
  • Chapter4 Specifications
    • 4.1 Electrical Characteristics
      • 4.1.1 DC Characteristics
        • Table 4.1 Absolute Maximum Stress Ratings
        • Table 4.2 Operating Conditions
        • Table 4.3 LVD Driver SCSI Signals—SD[15:0]±, SDP[1:0]±, SCD±, SIO±, SMSG±, SREQ±, SACK±, SBSY±, S...
        • Figure4.1 LVD Driver
        • Table 4.4 LVD Receiver SCSI Signals—SD[15:0]±, SDP[1:0]±, SCD±, SIO±, SMSG±, SREQ±, SACK±, SBSY±,...
        • Figure4.2 LVD Receiver
        • Table 4.5 Bidirectional SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/, SD[15:0]±, SDP[1:0]±, SR...
        • Table 4.6 Bidirectional SCSI Control Signals—SCD/, SIO/, SMSG/, SBSY/, SATN/, SSEL/, SRST/, SCD±,...
        • Table 4.7 DIFFSENS SCSI Signal
        • Table 4.8 Input Capacitance
        • Table 4.9 Input Control Signals—CLOCK, CHIP_RESET/, WS_ENABLE/
        • Table 4.10 Output Control Signals—BSY_LED, XFER_ACTIVE
      • 4.1.2 TolerANT Technology Electrical Characteristics
        • Table 4.11 TolerANT Technology Electrical Characteristics (Cont.)
        • Figure4.3 Rise and Fall Time Test Conditions
      • 4.1.3 AC Characteristics
        • Table 4.12 Clock Timing
        • Figure4.4 Clock Timing
    • 4.2 Chip Drawings
      • 4.2.1 Mechanical Drawing
        • Figure4.5 272-Ball-Count PBGA (VG) Mechanical Drawing (Sheet 1 of 2)
      • 4.2.2 BGA Drawing
        • Figure4.6 LSI53C320 272-Ball BGA Top View
  • AppendixA Wiring Diagrams
    • A.1 LSI53C320 Wiring Diagrams
      • FigureA.1 LSI53C320 Wiring Diagram 1 of 4
      • FigureA.2 LSI53C320 Wiring Diagram 2 of 4
      • FigureA.3 LSI53C320 Wiring Diagram 3 of 4
      • FigureA.4 LSI53C320 Wiring Diagram 4 of 4
  • AppendixB Glossary
  • Index
  • Customer Feedback