Document Outline

• 1. Pin Description
• 2. Characteristics and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • DAC Analog Characteristics - Commercial (-CQZ)
  • DAC Analog Characteristics - Automotive (-DQZ)
  • Power and Thermal Characteristics
  • Combined Interpolation & On-chip Analog Filter Response
  • Combined Interpolation & On-chip Analog Filter Response (CONTINuED)
  • DSD Combined Digital & On-chip Analog Filter Response
  • Digital Characteristics
  • Switching Characteristics - PCM
    • Figure 1. TDM Serial Audio Interface Timing
    • Figure 2. Serial Audio Interface Timing
  • Switching Characteristics - DSD
    • Figure 3. Direct Stream Digital - Serial Audio Input Timing
    • Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode
  • Switching Characteristics - Control Port - I²C Format
    • Figure 5. Control Port Timing - I²C Format
  • Switching Characteristics - Control Port - SPI Format
    • Figure 6. Control Port Timing - SPI Format
• 3. Typical Connection Diagram
  • Figure 7. Typical Connection Diagram, Software Mode
  • Figure 8. Typical Connection Diagram, Hardware
• 4. Applications
  • 4.1 Master Clock
    • Table 1. Single-Speed Mode (SSM) Standard Frequencies
    • Table 2. Double-Speed Mode (DSM) Standard Frequencies
    • Table 3. Quad-Speed Mode (QSM) Standard Frequencies
  • 4.2 Mode Select
    • Table 4. PCM Digital Interface Format, Hardware Mode Options
    • Table 5. Mode Selection, Hardware Mode Options
    • Table 6. Direct Stream Digital (DSD), Hardware Mode Options
  • 4.3 Digital Interface Formats
    • Figure 9. Format 0 - Left-Justified up to 24-bit Data
    • Figure 10. Format 1 - I²S up to 24-bit Data
    • Figure 11. Format 2 - Right-Justified 16-bit Data
    • Figure 12. Format 4 - Right-Justified 20-bit Data
    • Figure 13. Format 5 - Right-Justified 18-bit Data
    • 4.3.1 OLM #1
      • Figure 14. Format 8 - One-Line Mode 1
    • 4.3.2 OLM #2
      • Figure 15. Format 9 - One-Line Mode 2
    • 4.3.3 OLM #3
      • Figure 16. Format 10 - One-Line Mode 3
    • 4.3.4 OLM #4
      • Figure 17. Format 11 - One Line Mode 4
    • 4.3.5 TDM
      • Figure 18. Format 3 - TDM Mode
  • 4.4 Oversampling Modes
  • 4.5 Interpolation Filter
  • 4.6 De-Emphasis
    • Figure 19. De-Emphasis Curve
  • 4.7 ATAPI Specification
    • Figure 20. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
  • 4.8 Direct Stream Digital (DSD) Mode
    • Figure 21. DSD Phase Modulation Mode Diagram
  • 4.9 Grounding and Power Supply Arrangements
    • 4.9.1 Capacitor Placement
  • 4.10 Analog Output and Filtering
    • Figure 22. Full-Scale Output
    • Figure 23. Recommended Output Filter
  • 4.11 The MUTEC Outputs
    • Figure 24. Recommended Mute Circuitry
  • 4.12 Recommended Power-Up Sequence
    • 4.12.1 Hardware Mode
    • 4.12.2 Software Mode
  • 4.13 Recommended Procedure for Switching Operational Modes
• 5. Control Port Interface
  • 5.1 MAP Auto Increment
  • 5.2 I²C Mode
    • 5.2.1 I²C Write
    • 5.2.2 I²C Read
      • Figure 25. Control Port Timing, I²C Mode
  • 5.3 SPI Mode
    • 5.3.1 SPI Write
      • Figure 26. Control Port Timing, SPI Mode
  • 5.4 Memory Address Pointer (MAP)
    • 5.4.1 INCR (Auto Map Increment Enable)
    • 5.4.2 MAP4-0 (Memory Address Pointer)
• 6. Register Quick Reference
• 7. Register Description
  • 7.1 Chip I.D. and Revision (Address 01h)
    • 7.1.1 Chip I.D. [Read Only]
    • 7.1.2 Chip Revision [Read Only]
  • 7.2 Mode Control 1 (Address 02h)
    • 7.2.1 Control Port Enable (CPEN)
    • 7.2.2 Freeze Controls (FREEZE)
    • 7.2.3 PCM/DSD Selection (DSD/PCM)
    • 7.2.4 DAC Pair Disable (DACx_DIS)
    • 7.2.5 Power Down (PDN)
  • 7.3 PCM Control (Address 03h)
    • 7.3.1 Digital Interface Format (DIF)
      • Table 7. Digital Interface Formats - PCM Mode
    • 7.3.2 Functional Mode (FM)
  • 7.4 DSD Control (Address 04h)
    • 7.4.1 DSD Mode Digital Interface Format (DSD_DIF)
      • Table 8. Digital Interface Formats - DSD Mode
    • 7.4.2 Direct DSD Conversion (DIR_DSD)
    • 7.4.3 Static DSD Detect (STATIC_DSD)
    • 7.4.4 Invalid DSD Detect (INVALID_DSD)
    • 7.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE)
    • 7.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN)
  • 7.5 Filter Control (Address 05h)
    • 7.5.1 Interpolation Filter Select (FILT_SEL)
  • 7.6 Invert Control (Address 06h)
    • 7.6.1 Invert Signal Polarity (Inv_xx)
  • 7.7 Group Control (Address 07h)
    • 7.7.1 Mutec Pin Control (MUTEC)
    • 7.7.2 Channel A Volume = Channel B Volume (Px_A=B)
    • 7.7.3 Single Volume Control (SNGLVOL)
  • 7.8 Ramp and Mute (Address 08h)
    • 7.8.1 Soft Ramp and Zero Cross Control (SZC)
    • 7.8.2 Soft Volume Ramp-Up After Error (RMP_UP)
    • 7.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)
    • 7.8.4 PCM Auto-Mute (PAMUTE)
    • 7.8.5 DSD Auto-Mute (DAMUTE)
    • 7.8.6 Mute Polarity and Detect (MUTEP1:0)
  • 7.9 Mute Control (Address 09h)
    • 7.9.1 Mute (MUTE_xx)
  • 7.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h)
    • 7.10.1 De-Emphasis Control (PX_DEM1:0)
    • 7.10.2 ATAPI Channel Mixing and Muting (ATAPI)
      • Table 9. ATAPI Decode Table
  • 7.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)
    • 7.11.1 Digital Volume Control (xx_VOL7:0)
      • Table 10. Example Digital Volume Settings
  • 7.12 PCM Clock Mode (Address 16h)
    • 7.12.1 Master Clock Divide by 2 Enable (MCLKDIV)
• 8. Filter Plots
  • Figure 27. Single-Speed (fast) Stopband Rejection
  • Figure 28. Single-Speed (fast) Transition Band
  • Figure 29. Single-Speed (fast) Transition Band (detail)
  • Figure 30. Single-Speed (fast) Passband Ripple
  • Figure 31. Single-Speed (slow) Stopband Rejection
  • Figure 32. Single-Speed (slow) Transition Band
  • Figure 33. Single-Speed (slow) Transition Band (detail)
  • Figure 34. Single-Speed (slow) Passband Ripple
  • Figure 35. Double-Speed (fast) Stopband Rejection
  • Figure 36. Double-Speed (fast) Transition Band
  • Figure 37. Double-Speed (fast) Transition Band (detail)
  • Figure 38. Double-Speed (fast) Passband Ripple
  • Figure 39. Double-Speed (slow) Stopband Rejection
  • Figure 40. Double-Speed (slow) Transition Band
  • Figure 41. Double-Speed (slow) Transition Band (detail)
  • Figure 42. Double-Speed (slow) Passband Ripple
  • Figure 43. Quad-Speed (fast) Stopband Rejection
  • Figure 44. Quad-Speed (fast) Transition Band
  • Figure 45. Quad-Speed (fast) Transition Band (detail)
  • Figure 46. Quad-Speed (fast) Passband Ripple
  • Figure 47. Quad-Speed (slow) Stopband Rejection
  • Figure 48. Quad-Speed (slow) Transition Band
  • Figure 49. Quad-Speed (slow) Transition Band (detail)
  • Figure 50. Quad-Speed (slow) Passband Ripple
• 9. Parameter Definitions
• 10. Package Dimensions
• 11. Ordering Information
• 12. References
• 13. Revision History