Document Outline

• 1. Pin Descriptions - Software (Hardware) Mode
  • 1.1 Digital I/O Pin Characteristics
    • Table 1. I/O Power Rails
• 2. Typical Connection Diagrams
  • Figure 1. Typical Connection Diagram (Software Mode)
  • Figure 2. Typical Connection Diagram (Hardware Mode)
• 3. Characteristic and Specification Tables
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • Analog Output Characteristics (Commercial - CNZ)
  • Analog Output Characteristics (Automotive - DNZ)
  • Line Output Voltage Characteristics
  • Headphone Output Power Characteristics
    • Figure 3. Headphone Output Test Load
  • Combined DAC Interpolation & on-Chip Analog FIlter Response
  • Switching Specifications - Serial Port
    • Figure 4. Serial Audio Interface Slave Mode Timing
    • Figure 5. Serial Audio Interface Master Mode Timing
  • Switching Specifications - I²C Control Port
    • Figure 6. Control Port Timing - I²C
  • Switching Characteristics - SPI Control Port
    • Figure 7. Control Port Timing - SPI Format
  • DC Electrical Characteristics
  • Digital Interface Specifications & Characteristics
  • Power Consumption
• 4. Applications
  • 4.1 Overview
    • 4.1.1 Architecture
    • 4.1.2 Line & Headphone Outputs
    • 4.1.3 Signal Processing Engine
    • 4.1.4 Beep Generator
    • 4.1.5 Device Control (Hardware or Software Mode)
    • 4.1.6 Power Management
  • 4.2 Hardware Mode
    • Table 2. Hardware Mode Feature Summary
  • 4.3 Analog Outputs
    • Figure 8. Output Architecture
    • 4.3.1 De-Emphasis Filter
      • Figure 9. De-Emphasis Curve
    • 4.3.2 Volume Controls
    • 4.3.3 Mono Channel Mixer
    • 4.3.4 Beep Generator
      • Figure 10. Beep Configuration Options
    • 4.3.5 Tone Control
    • 4.3.6 Limiter
      • Figure 11. Peak Detect & Limiter
    • 4.3.7 Line-Level Outputs and Filtering
    • 4.3.8 On-Chip Charge Pump
  • 4.4 Serial Port Clocking
    • 4.4.1 Slave
      • Table 3. MCLK/LRCK Ratios
    • 4.4.2 Master
      • Figure 12. Master Mode Timing
    • 4.4.3 High-Impedance Digital Output
      • Figure 13. Tri-State SCLK/LRCK
    • 4.4.4 Quarter- and Half-Speed Mode
  • 4.5 Digital Interface Formats
    • Figure 14. I²S Format
    • Figure 15. Left-Justified Format
    • Figure 16. Right-Justified Format (DAC only)
  • 4.6 Initialization
  • 4.7 Recommended Power-Up Sequence
  • 4.8 Recommended Power-Down Sequence
    • Figure 17. Initialization Flow Chart
  • 4.9 Software Mode
    • 4.9.1 SPI Control
      • Figure 18. Control Port Timing in SPI Mode
    • 4.9.2 I²C Control
      • Figure 19. Control Port Timing, I²C Write
      • Figure 20. Control Port Timing, I²C Read
    • 4.9.3 Memory Address Pointer (MAP)
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
  • 6.2 Power Control 1 (Address 02h)
  • 6.3 Speed Control (Address 03h)
  • 6.4 Interface Control (Address 04h)
  • 6.5 DAC Output Control (Address 08h)
  • 6.6 DAC Control (Address 09h)
  • 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)
  • 6.8 Beep Frequency & Timing Configuration (Address 12h)
  • 6.9 Beep Off Time & Volume (Address 13h)
  • 6.10 Beep Configuration & Tone Configuration (Address 14h)
  • 6.11 Tone Control (Address 15h)
  • 6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)
  • 6.13 PCM Channel Mixer (Address 18h)
  • 6.14 Limiter Threshold SZC Disable (Address 19h)
  • 6.15 Limiter Release Rate Register (Address 1Ah)
  • 6.16 Limiter Attack Rate Register (Address 1Bh)
  • 6.17 Status (Address 20h) (Read Only)
  • 6.18 Charge Pump Frequency (Address 21h)
• 7. Analog Performance Plots
  • 7.1 Headphone THD+N versus Output Power Plots
    • Figure 21. THD+N vs. Output Power per Channel at 1.8 V (16 W load)
    • Figure 22. THD+N vs. Output Power per Channel at 2.5 V (16 W load)
    • Figure 23. THD+N vs. Output Power per Channel at 1.8 V (32 W load)
    • Figure 24. THD+N vs. Output Power per Channel at 2.5 V (32 W load)
  • 7.2 Headphone Amplifier Efficiency
    • Figure 25. Power Dissipation vs. Output Power into Stereo 16 W
    • Figure 26. Power Dissipation vs. Output Power into Stereo 16 W (Log Detail)
• 8. Example System Clock Frequencies
  • 8.1 Auto Detect Enabled
  • 8.2 Auto Detect Disabled
• 9. PCB Layout Considerations
  • 9.1 Power Supply, Grounding
  • 9.2 QFN Thermal Pad
• 10. Digital Filters
  • Figure 27. Passband Ripple
  • Figure 28. Stopband
  • Figure 29. Transition Band
  • Figure 30. Transition Band (Detail)
• 11. Parameter Definitions
• 12. References
• 13. Package Dimensions
  • Thermal Characteristics
• 14. Ordering Information
• 15. Revision History