Document Outline

• Intel® PXA26x Processor Family
• Introduction 1
  • 1.1 Intel® XScale™ Core Features
  • 1.2 System Integration Features
    • 1.2.1 Memory Controller
    • 1.2.2 Clocks and Power Controllers
    • 1.2.3 Universal Serial Bus (USB) Client
    • 1.2.4 Direct Memory Access Controller (DMAC)
    • 1.2.5 Liquid Crystal Display (LCD) Controller
    • 1.2.6 AC97 Controller
    • 1.2.7 Inter-Integrated Circuit Sound (I2S) Controller
    • 1.2.8 Multimedia Card (MMC) Controller
    • 1.2.9 Fast Infrared (FIR) Communication Port
    • 1.2.10 Synchronous Serial Protocol Controller (SSPC)
    • 1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit
    • 1.2.12 General Purpose Input/Output (GPIO)
    • 1.2.13 Universal Asynchronous Receiver/Transmitters (UARTs)
    • 1.2.14 Real-Time Clock (RTC)
    • 1.2.15 Operating System (OS) Timers
    • 1.2.16 Pulse-Width Modulator (PWM)
    • 1.2.17 Interrupt Controller
    • 1.2.18 Integrated Synchronous Flash
    • 1.2.19 Single-ended Universal Serial Bus Client interface
    • 1.2.20 Network Synchronous Serial Protocol Port
    • 1.2.21 Audio Synchronous Serial Protocol Port
    • 1.2.22 Hardware UART (HWUART)
• System Architecture 2
  • 2.1 Overview
    • Figure 2-1. Block Diagram
  • 2.2 Package Types
  • 2.3 Intel® XScale™ Microarchitecture Implementation Options
    • 2.3.1 CPU Core Fault Register - PSFS Bit
      • Table 2-1. CPU Core Fault Register Bitmap
    • 2.3.2 Coprocessor 14 Registers 0-3 - Performance Monitoring
    • 2.3.3 Coprocessor 14 Register 6 and 7- Clock and Power Management
    • 2.3.4 Coprocessor 15 Register 0 - ID Register Definition
      • Table 2-2. ID Register Bitmap and Bit Definitions (Read-only) (Sheet 1 of 2)
      • Table 2-3. PXA26x processor family ID Values
    • 2.3.5 Coprocessor 15 Register 1 - P-Bit
  • 2.4 Input/Output Ordering
  • 2.5 Semaphores
    • Note: Semaphore coherency may be interrupted because an external companion chip that uses the MBREQ/MBGNT handshake can take own...
  • 2.6 Interrupts
    • Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an interrupt service routine (ISR), clear the interrupt early in the routine.
  • 2.7 Reset
    • Table 2-4. Effect of Each Type of Reset on Internal Register State
  • 2.8 Internal Registers
  • 2.9 Selecting Peripherals vs. General Purpose Input/ Output
  • 2.10 Power on Reset and Boot Operation
  • 2.11 Power Management
    • Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an external device in confli...
  • 2.12 Pin List
    • Table 2-5. Processor Pin Types
    • Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 1 of 12)
    • Table 2-7. Pin Description Notes
  • 2.13 Register Address Summary
    • Table 2-8. Register Address Summary (Sheet 1 of 13)
  • 2.14 Memory Map
    • Note: Accessing reserved portions of the memory map gives unpredictable results.
    • Figure 2-2. Memory Map (Part One) - From 0x8000 0000 to 0xFFFF FFFF
    • Figure 2-3. Memory Map (Part Two) - From 0x0000 0000 to 0x7FFF FFFF
• Clocks and Power Manager 3
  • 3.1 Clock Manager Introduction
  • 3.2 Power Manager Introduction
  • 3.3 Clock Manager
    • 3.3.1 32.768-KHz Oscillator
    • 3.3.2 3.6864-MHz Oscillator
    • 3.3.3 Core Phase Locked Loop
    • 3.3.4 95.85-MHz Peripheral Phase Locked Loop
    • 3.3.5 147.46-MHz Peripheral Phase Locked Loop
    • 3.3.6 Clock Gating
  • 3.4 Resets and Power Modes
    • 3.4.1 Hardware Reset
      • 3.4.1.1 Invoking Hardware Reset
      • 3.4.1.2 Behavior During Hardware Reset
      • 3.4.1.3 Completing Hardware Reset
    • 3.4.2 Watchdog Reset
      • 3.4.2.1 Invoking Watchdog Reset
      • 3.4.2.2 Behavior During Watchdog Reset
      • 3.4.2.3 Completing Watchdog Reset
    • 3.4.3 GPIO Reset
      • 3.4.3.1 Invoking GPIO Reset
      • 3.4.3.2 Behavior During GPIO Reset
      • 3.4.3.3 Completing GPIO Reset
    • 3.4.4 Run Mode
    • 3.4.5 Turbo Mode
      • 3.4.5.1 Entering Turbo Mode
      • 3.4.5.2 Behavior in Turbo Mode
      • 3.4.5.3 Exiting Turbo Mode
    • 3.4.6 Idle Mode
      • 3.4.6.1 Entering Idle Mode
      • 3.4.6.2 Behavior in Idle Mode
      • 3.4.6.3 Exiting Idle Mode
    • 3.4.7 33-MHz Idle Mode
      • 3.4.7.1 Entering 33-MHz Idle Mode
      • 3.4.7.2 Behavior in 33-MHz Idle Mode
      • 3.4.7.3 Exiting 33-MHz Idle Mode
    • 3.4.8 Frequency Change Sequence
      • 3.4.8.1 Preparing for the Frequency Change Sequence
      • 3.4.8.2 Starting the Frequency Change Sequence
      • 3.4.8.3 Behavior During the Frequency Change Sequence
      • 3.4.8.4 Completing the Frequency Change Sequence
    • 3.4.9 Sleep Mode
      • 3.4.9.1 Sleep Mode External Voltage Regulator Requirements
      • 3.4.9.2 Preparing for Sleep Mode
      • 3.4.9.3 Entering Sleep Mode
      • 3.4.9.4 Behavior in Sleep Mode
      • 3.4.9.5 Exiting Sleep Mode
    • 3.4.10 Power Mode Summary
  • 3.5 Power Manager Registers
    • 3.5.1 Power Manager Control Register (PMCR)
    • 3.5.2 Power Manager General Configuration Register (PCFR)
    • 3.5.3 Power Manager Wake-Up Enable Register (PWER)
    • 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
    • 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)
    • 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)
    • 3.5.7 Power Manager Sleep Status Register (PSSR)
    • 3.5.8 Power Manager Scratch Pad Register (PSPR)
    • 3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR)
    • 3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)
    • 3.5.11 Reset Controller Status Register (RCSR)
    • 3.5.12 Power Manager Register Locations
  • 3.6 Clocks Manager Registers
    • 3.6.1 Core Clock Configuration Register (CCCR)
    • 3.6.2 Clock Enable Register (CKEN)
    • 3.6.3 Oscillator Configuration Register (OSCC)
    • 3.6.4 Clocks Manager Register Locations
  • 3.7 Coprocessor 14: Clock and Power Management
    • 3.7.1 Core Clock Configuration Register (CCLKCFG)
    • 3.7.2 Power Mode Register (PWRMODE)
  • 3.8 External Hardware Considerations
    • 3.8.1 Power-On-Reset Considerations
    • 3.8.2 Driving the Crystal Pins from an External Clock Source
    • 3.8.3 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator
• System Integration Unit 4
  • 4.1 General-Purpose Input/Output
    • 4.1.1 GPIO Operation
      • Warning: GPIOs [89:86], behave differently. They have different default values on reset. On reset, these four GPIOs are outputs....
        • Figure 4-1. General-Purpose I/O Block Diagram
    • 4.1.2 GPIO Alternate Functions
      • Table 4-1. GPIO Alternate Functions (Sheet 1 of 5)
    • 4.1.3 GPIO Register Definitions
      • Table 4-2. GPIO Register Definitions (Sheet 1 of 2)
        • Note: GPLR2[31:26], GPSR2[31:26], GPCR2[31:26], GPDR2[31:26], GRER2[31:26], GFER2[31:26], GEDR2[31:26] and GAFR2_U[31:21] are reserved bits. Write zeros to these bits and ignore all reads from these bits.
      • 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
        • Table 4-3. GPLR0 Bit Definitions
        • Table 4-4. GPLR1 Bit Definitions
        • Table 4-5. GPLR2 Register Bitmap
      • 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
        • Note: A reset clears all bits in the GPDR0-2 registers and configures GPIO[85:0] as inputs and GPIO[89:86] as outputs.
        • Table 4-6. GPDR0 Bit Definitions
        • Table 4-7. GPDR1 Bit Definitions
        • Table 4-8. GPDR2 Register Bitmap
      • 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (GPCR0, GPCR1, GPCR2)
        • Table 4-9. GPSR0 Bit Definitions
        • Table 4-10. GPSR1 Bit Definitions
        • Table 4-11. GPSR2 Register Bitmap
        • Table 4-12. GPCR0 Bit Definitions
        • Table 4-13. GPCR1 Bit Definitions
        • Table 4-14. GPCR2 Register Bitmap
      • 4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2) and Falling Edge Detect Enable Registers (GFER0, GFER1, GFER2)
        • Note: The minimum pulse width duration to guarantee edge detection is 1mS.
        • Note: For reserved bits in GRER2 and GFER2, writes must be zeros and reads must be ignored.
        • Table 4-15. GRER0 Bit Definitions
        • Table 4-16. GRER1 Bit Definitions
        • Table 4-17. GRER2 Register Bitmap
        • Table 4-18. GFER0 Bit Definitions
        • Table 4-19. GFER1 Bit Definitions
        • Table 4-20. GFER2 Register Bitmap
      • 4.1.3.5 GPIO Edge Detect Status Register (GEDR)
        • Table 4-21. GEDR0 Bit Definitions
        • Table 4-22. GEDR1 Bit Definitions
        • Table 4-23. GEDR2 Register Bitmap
      • 4.1.3.6 GPIO Alternate Function Register (GAFR)
        • Warning: Configuring a GPIO to map to an alternate function that is not available causes indeterminate results.
        • Table 4-24. GAFR0_L Bit Definitions
        • Table 4-25. GAFR0_U Bit Definitions
        • Table 4-26. GAFR1_L Bit Definitions
        • Table 4-27. GAFR1_U Bit Definitions
        • Table 4-28. GAFR2_L Bit Definitions
        • Table 4-29. GAFR2_U Register Bitmap
      • 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers
        • Note: For more information on alternate functions, refer to the Source Unit column in Table 4-1 for the appropriate section of this document.
    • 4.1.4 GPIO Register Locations
      • Table 4-30. GPIO Register Addresses (Sheet 1 of 2)
  • 4.2 Interrupt Controller
    • 4.2.1 Interrupt Controller Operation
      • Figure 4-2. Interrupt Controller Block Diagram
    • 4.2.2 Interrupt Controller Register Definitions
      • 4.2.2.1 Interrupt Controller Mask Register (ICMR)
        • Table 4-31. ICMR Register Bitmap
      • 4.2.2.2 Interrupt Controller Level Register (ICLR)
        • Table 4-32. ICLR Register Bitmap
      • 4.2.2.3 Interrupt Controller Control Register (ICCR)
        • Note: This register is cleared during all resets.
        • Table 4-33. ICCR Bit Definitions
      • 4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)
        • Table 4-34. ICIP Register Bitmap
        • Table 4-35. ICFP Register Bitmap
      • 4.2.2.5 Interrupt Controller Pending Register (ICPR)
        • Table 4-36. ICPR Register Bitmap (Sheet 1 of 3)
        • Table 4-37. List of First-Level Interrupts (Sheet 1 of 2)
    • 4.2.3 Interrupt Controller Register Locations
      • Table 4-38. Interrupt Controller Register Addresses
  • 4.3 Real-Time Clock (RTC)
    • 4.3.1 Real-Time Clock Operation
      • Note: Without trimming, a typical 50ppm oscillator only provides an accuracy of +/- 5 seconds per day.
    • 4.3.2 Real-Time Clock Register Definitions
      • 4.3.2.1 Real-Time Clock Trim Register (RTTR)
        • Table 4-39. RTTR Bit Definitions
      • 4.3.2.2 Real-Time Clock Alarm Register (RTAR)
        • Table 4-40. RTAR Bit Definitions
      • 4.3.2.3 Real-Time Clock Counter Register (RCNR)
        • Table 4-41. RCNR Bit Definitions
      • 4.3.2.4 Real-Time Clock Status Register (RTSR)
        • Table 4-42. RTSR Bit Definitions
    • 4.3.3 Trim Procedure
      • 4.3.3.1 Oscillator Frequency Calibration
      • 4.3.3.2 RTTR Value Calculations
    • 4.3.4 Real-Time Clock Register Locations
      • Table 4-43. RTC Register Addresses
  • 4.4 Operating System Timer
    • 4.4.1 Watchdog Timer Operation
      • 1. The current value of the counter is read.
      • 2. An offset is then added to the read value. This offset corresponds to the amount of time before the next time-out (care must be taken to account for counter wraparound).
      • 3. The updated value is written back to OSMR3.
    • 4.4.2 Operating System Timer Register Definitions
      • 4.4.2.1 Operating System Timer Match Register 0-3 (OSMR0, OSMR1, OSMR2, OSMR3)
        • Table 4-44. OSMR[x] Bit Definitions
      • 4.4.2.2 Operating System Timer Interrupt Enable Register (OIER)
        • Table 4-45. OIER Bit Definitions
      • 4.4.2.3 Operating System Timer Watchdog Match Enable Register (OWER)
        • Table 4-46. OWER Bit Definitions
      • 4.4.2.4 Operating System Timer Count Register (OSCR)
        • Table 4-47. OSCR Bit Definitions
      • 4.4.2.5 Operating System Timer Status Register (OSSR)
        • Table 4-48. OSSR Bit Definitions
    • 4.4.3 Operating System Timer Register Locations
      • Table 4-49. OS Timer Register Locations
  • 4.5 Pulse Width Modulator
    • 4.5.1 Pulse Width Modulator Operation
      • Figure 4-3. PWMn Block Diagram
      • 4.5.1.1 Interdependencies
        • Note: Take care to ensure that the value of the PWM_PERVALn register remains larger than PWM_DUTYn register. In the case where PWM_PERVALn is less than PWM_DUTYn the output maintains a high state.
      • 4.5.1.2 Reset Sequence
      • 4.5.1.3 Power Management Requirements
    • 4.5.2 Register Descriptions
      • 4.5.2.1 PWM Control Registers (PWM_CTRLn)
        • Note: The value of the divisor is one greater than the value programmed into the PRESCALE field.
        • Note: During abrupt shut down the PWM_OUTn signal may be delayed by up to one PSCLK_PWMn clock period.
        • Table 4-50. PWM_CTRLn Bit Definitions
      • 4.5.2.2 PWM Duty Cycle Registers (PWM_DUTYn)
        • Note: If FDCYCLE is 0b1, PWM_OUTn is high for the entire period and is not influenced by the value programmed in the DCYCLE bits.
        • Table 4-51. PWM_DUTYn Bit Definitions
      • 4.5.2.3 PWM Period Control Register (PWM_PERVALn)
        • Note: Due to internal timing requirements, all changes to any of the PWM registers must be complete a minimum of 4 core clock cy...
        • Table 4-52. PWM_PERVALn Bit Definitions
    • 4.5.3 Pulse Width Modulator Output Wave Example
      • Figure 4-4. Basic Pulse Width Waveform
    • 4.5.4 Register Summary
      • Table 4-53. PWM Register Locations
• Direct Memory Access Controller 5
  • 5.1 Direct Memory Access Description
    • Figure 5-1. DMAC Block Diagram
    • 5.1.1 Direct Memory Access Controller Channels
    • 5.1.2 Signal Descriptions
      • Table 5-1. DMAC Signal List
      • 5.1.2.1 DREQ[1:0] and PREQ[37:0] Signals
        • Figure 5-2. DREQ timing requirements
      • 5.1.2.2 DMA_IRQ Signal
    • 5.1.3 Direct Memory Access Channel Priority Scheme
      • Table 5-2. Channel Priority (if all channels are running concurrently)
      • Table 5-3. Channel Priority
      • Table 5-4. Priority Schemes Examples
    • 5.1.4 Direct Memory Access Descriptors
      • 5.1.4.1 No-Descriptor Fetch Mode
        • 1. The channel is in an uninitialized state after reset.
        • 2. The DCSR[RUN] bit is set to a 0 and the DCSR[NODESCFETCH] bit is set to a 1.
        • 3. The software writes a source address to the DSADR register, a target address to the DTADR register, and a command to the DCMD register. The DDADR register is reserved in this No- Descriptor Fetch Mode and must not be written.
        • 4. The software writes a 1 to the DCSR[RUN] bit and the No-Descriptor fetches are performed.
        • 5. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits.
        • 6. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and DCMD[LENGTH].
        • 7. The channel waits for the next request or continues with the data transfer until the DCMD[LENGTH] reaches zero.
        • 8. The DDADR[STOP] is set to a 1 and the channel stops.
        • Figure 5-3. No-Descriptor Fetch Mode Channel State
      • 5.1.4.2 Descriptor Fetch Mode
        • 1. The channel is in an uninitialized state after reset.
        • 2. The software writes a descriptor address (aligned to a 16-byte boundary) to the DDADR register.
        • 3. The software writes a 1 to the DCSR[RUN] bit.
        • 4. The DMAC fetches the four-word descriptor (assuming that the memory is already set up with the descriptor chain) from the memory indicated by DDADR.
        • 5. The four-word DMA descriptor, aligned on a 16-byte boundary in main memory, loads the these registers:
        • 6. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits.
        • 7. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and DCMD[LENGTH].
        • 8. The channel waits for the next request or continues with the data transfer until the DCMD[LENGTH] reaches zero.
        • 9. The channel stops or continues with a new descriptor fetch from the memory, as determined by the DDADR[STOP] bit.
        • Figure 5-4. Descriptor Fetch Mode Channel State
      • 5.1.4.3 Servicing an Interrupt
    • 5.1.5 Channel States
    • 5.1.6 Read and Write Order
    • 5.1.7 Byte Transfer Order
      • 1. Byte[0]
      • 2. Byte[1]
      • 3. Byte[2]
      • 4. Byte[3]
      • Figure 5-5. Little Endian Transfers
    • 5.1.8 Trailing Bytes
      • 1. Writing a 0 to the DCSR[RUN] bit to stop the DMA channel.
      • 2. Wait until the channel to stops.
      • 3. Make reads to the channel’s registers to check the channel’s status.
      • 4. Perform the programmed I/O transfers to the peripheral.
      • 5. Set the DCSR[RUN] bit to a 1 and reset the DMA channel for future data transfers.
  • 5.2 Transferring Data
    • 5.2.1 Servicing Internal Peripherals
      • 5.2.1.1 Using Flow-Through DMA Read Cycles to Service Internal Peripherals
        • 1. The DMAC sends the memory controller a request to read the number of bytes addressed by DSADRx[31:0] into a 32-byte staging buffer in the DMAC.
        • 2. The DMAC transfers the data to the I/O device addressed in DTADRx[31:0]. DCMD[WIDTH] specifies the width of the internal peripheral to which the data is transferred.
        • 3. At the end of the transfer, DSADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same value.
      • 5.2.1.2 Using Flow-Through DMA Write Cycles to Service Internal Peripherals
        • 1. The DMAC transfers the required number of bytes from the I/O device addressed by DSADRx[31:0] to the DMAC write buffer.
        • 2. The DMAC transfers the data to the memory controller via the internal bus. DCMD[WIDTH] specifies the width of the internal peripheral to which the transfer is being made.
        • 3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number.
    • 5.2.2 Quick Reference for Direct Memory Access Programming
      • Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 1 of 2)
    • 5.2.3 Servicing Companion Chips and External Peripherals
      • 5.2.3.1 Using Flow-Through DMA Read Cycles to Service External Peripherals
        • 1. The DMAC sends a request to the memory controller to read the number of bytes addressed by DSADRx[31:0] into a 32-byte staging buffer in the DMAC.
        • 2. The DMAC transfers the data in the buffer to the external device addressed in DTADRx[31:0].
        • 3. At the end of the transfer, DSADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same value.
        • Note: The process shown for a flow-through DMA read to an external peripheral indicates that the external address increases. Some external peripherals, such as FIFOs, do not require an increment in the external address.
      • 5.2.3.2 Using Flow-Through DMA Write Cycles to Service External Peripherals
        • 1. The DMAC transfers the required number of bytes from the I/O device addressed by DSADRx[31:0] to the DMAC write buffer.
        • 2. The DMAC transfers the data to the memory controller via the internal bus.
        • 3. At the end of the transfer, DTADRx is increased by the smaller value of DCMDx[LENGTH] and DCMD[SIZE]. DCMDx[LENGTH] is decreased by the same number.
        • Note: The process shown for a flow-through DMA write to an external peripheral indicates that the external address increases. Some external peripherals, such as FIFOs, do not require an increment in the external address.
    • 5.2.4 Memory-to-Memory Moves
      • 1. The processor writes to the DCSR[RUN] register bit and starts the memory-to-memory moves.
      • 2. If the processor is in the Descriptor Fetch Mode, the channel configured for the move fetches the four-word descriptor. The c...
      • 3. The DMAC sends a request to the memory controller to read the number of bytes addressed by DSADRx[31:0] into a 32-byte staging buffer in the DMAC.
      • 4. The DMAC generates a write cycle to the location addressed in DTADRx[31:0].
      • 5. At the end of the transfer, DSADRx and DTADRx are increased by the smaller value of DCMD[SIZE] and DCMDx[LENGTH]. If DCMD[SIZ...
      • Note: The process shown for a memory-to-memory transfer indicates that the external address increases. Some external peripherals, such as FIFOs, do not require an increment in the external address.
  • 5.3 Direct Memory Access Controller Registers
    • 5.3.1 DMA Interrupt Register
      • Table 5-6. DINT Register Bitmap and Bit Definitions
    • 5.3.2 DMA Channel Control/Status Register
      • Table 5-7. DMA Channel Control/Status Register Bitmap and Bit Definitions (Sheet 1 of 2)
    • 5.3.3 DMA Request to Channel Map Registers
      • Table 5-8. DRCMRx Registers Bitmap Bit Definitions
    • 5.3.4 DMA Descriptor Address Registers
      • Table 5-9. DMA Descriptor Address Register Bit Definitions
    • 5.3.5 DMA Source Address Registers
      • Table 5-10. DSADRx Register Bitmap Bit Definitions
    • 5.3.6 DMA Target Address Registers
      • Table 5-11. DTADRx Register Bitmap Bit Definitions
    • 5.3.7 DMA Command Registers
      • Table 5-12. DCMDx Register Bitmap and Bit Definitions (Sheet 1 of 2)
  • 5.4 Examples
    • Example 5-1. How to set up and start a channel:
    • Example 5-2. How to initialize a descriptor list for a channel that is running:
    • Example 5-3. How to add a descriptor to the end of a descriptor list for a channel that is running:
      • 1. Write a 0 to DCSR[RUN].
      • 2. Wait until the channel stops. The channel stop state is reflected in the DCSR:STOPSTATE bit.
      • 3. In memory, create the descriptor to be added and set its stop bit to a 1.
      • 4. In the memory, manipulate the DDADR of the current chain’s last descriptor such that its DDADR points to the descriptor created in Step 3.
      • 5. In the memory, create a new descriptor that has the same DDADR, DSADR, DTADR, and CMD as those of the stopped DMA channel. The new descriptor is the next descriptor for the list.
      • 6. Examine the DMA channel registers and determine if the channel stopped in the chain’s last descriptor of the chain. If it did...
      • 7. Program the channel’s DDADR with the descriptor created in Step 5.
      • 8. Set the DCSR[RUN] to a 1.
    • Example 5-4. How to initialize a channel that is going to be used by a direct DMA master:
      • 1. When the companion chip asserts DREQ from 0 to 1, the DMA must fetch four words of the descriptor from one of the chip’s ports.
      • 2. Based on the information contained in the four descriptor words, the DMA must transfer data from the source address to the destination address without waiting for another request from the companion chip.
      • 3. After it transfers the number of bytes in DCMD:LENGTH, the DMA returns to Step 1.
  • 5.5 Direct Memory Access Controller Registers Locations
    • Table 5-13. DMA Controller Registers (Sheet 1 of 4)
• Memory Controller 6
  • 6.1 Overview
    • Figure 6-1. General Memory Interface Configuration
  • 6.2 Functional Description
    • 6.2.1 SDRAM Interface Overview
    • 6.2.2 Static Memory Interface / Variable Latency I/O Interface
    • 6.2.3 16-Bit PC Card / Compact Flash Interface
  • 6.3 Memory System Examples
    • Figure 6-2. SDRAM Memory System Example
    • Figure 6-3. Asynchronous Static Memory System Example
  • 6.4 Memory Accesses
    • Table 6-1. Device Transactions
    • 6.4.1 Reads and Writes
    • 6.4.2 Aborts and Nonexistent Memory
  • 6.5 Memory Configuration Registers
    • Table 6-2. Memory Interface Control Registers
  • 6.6 Synchronous DRAM Memory Interface
    • 6.6.1 SDRAM MDCNFG Register
      • Table 6-3. MDCNFG Register Bitmap and Bit Definitions (Sheet 1 of 3)
    • 6.6.2 SDRAM Mode Register Set Configuration Register
      • Table 6-4. MDMRS Register Bitmap (Sheet 1 of 2)
      • 6.6.2.1 Low-Power SDRAM Mode Register Set Configuration Register
        • Table 6-5. MDMRSLP Register Bit Definitions
    • 6.6.3 SDRAM MDREFR Register
      • Table 6-6. MDREFR Register Bitmap (Sheet 1 of 3)
    • 6.6.4 SDRAM Memory Options
      • Table 6-7. Sample SDRAM Memory Size Options
      • 6.6.4.1 SDRAM Addressing Modes
        • Figure 6-4. External to Internal Address Mapping Options
        • Table 6-8. External to Internal Address Mapping for Normal Bank Addressing (Sheet 1 of 2)
        • Table 6-9. External to Internal Address Mapping for SA-1111 Addressing (Sheet 1 of 2)
        • Table 6-10. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3)
        • Table 6-11. Pin Mapping to SDRAM Devices with SA-1111 Addressing (Sheet 1 of 2)
    • 6.6.5 SDRAM Command Overview
      • Table 6-12. SDRAM Command Encoding
      • Table 6-13. SDRAM Mode Register Opcode Table
    • 6.6.6 SDRAM Waveforms
      • Figure 6-5. SDRAM Read
      • Figure 6-6. SDRAM Read With a Second Read to Same Bank, Same Row
      • Figure 6-7. SDRAM Read With a Second Read to Same Bank, Different Row
      • Figure 6-8. SDRAM Read With a Second Read to a Different Bank
      • Figure 6-9. SDRAM Write
      • Figure 6-10. SDRAM Write With a Second Write to Same Bank, Same Row
  • 6.7 Synchronous Static Memory Interface
    • 6.7.1 Synchronous Static Memory Configuration Register
      • Table 6-14. SXCNFG Register Bitmap (Sheet 1 of 6)
      • Table 6-15. SXCNFG Register Bitmap
      • 6.7.1.1 SMROM Memory Options
        • Table 6-16. Synchronous Static Memory External to Internal Address Mapping Options (Sheet 1 of 2)
    • 6.7.2 Synchronous Static Memory Mode Register Set Configuration Register
      • Table 6-17. SXMRS Register Bitmap
    • 6.7.3 Synchronous Static Memory Timing Diagrams
      • Figure 6-11. SMROM Read Timing Diagram Half-Memory Clock Frequency,
    • 6.7.4 Non-SDRAM Timing SXMEM Operation
      • Table 6-18. Read Configuration Register Programming Values
      • Table 6-19. Frequency Code Configuration Values Based on Clock Speed (Sheet 1 of 2)
      • 6.7.4.1 Non-SDRAM Timing Flash Read Timing Diagram
        • Figure 6-12. Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode)
  • 6.8 Asynchronous Static Memory
    • 6.8.1 Static Memory Interface
      • Table 6-20. 32-Bit Bus Write Access (Sheet 1 of 2)
      • Table 6-21. 16-Bit Bus Write Access
      • 6.8.1.1 Static Memory SA-1111 Compatibility Configuration Register (SA1111CR)
        • Table 6-22. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]
        • Table 6-23. 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]
        • Table 6-24. SA-1111 Register Bit Definitions
    • 6.8.2 Asynchronous Static Memory Control Registers (MSC0 - 2)
      • Table 6-25. MSC0/1/2 Register Bit Definitions (Sheet 1 of 3)
        • Figure 6-13. MSC0/1/2 Register Bitmap
      • Table 6-26. Asynchronous Static Memory and Variable Latency I/O Capabilities (Sheet 1 of 2)
    • 6.8.3 ROM Interface
      • 6.8.3.1 ROM Timing Diagrams and Parameters
        • Figure 6-14. 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0:RDF = 4, MSC0:RDN = 1, MSC0:RRR = 1)
        • Figure 6-15. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash (MSC0:RDF = 4, MSC0:RDN = 1, MSC0:RRR = 0)
        • Figure 6-16. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data Beats (MSC0:RDF = 4, MSC0:RRR = 1)
    • 6.8.4 SRAM Interface Overview
      • 6.8.4.1 SRAM Timing Diagrams and Parameters
        • Figure 6-17. 32-Bit SRAM Write Timing Diagram (4-beat Burst) (MSC0:RDN = 2, MSC0:RRR = 1)
    • 6.8.5 Variable Latency I/O (VLIO) Interface Overview
      • 6.8.5.1 Variable Latency I/O Timing Diagrams and Parameters
        • Figure 6-18. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat) (MSC0:RDF = 2, MSC0:RDN = 2, MSC0:RRR = 1)
        • Figure 6-19. 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles Per Beat)
    • 6.8.6 FLASH Memory Interface
      • 6.8.6.1 Flash Memory Timing Diagrams and Parameters
        • Figure 6-20. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)
  • 6.9 16-Bit PC Card/Compact Flash Interface
    • 6.9.1 Expansion Memory Timing Configuration Register
      • Table 6-27. MCMEMx Register Bitmap
        • Figure 6-21. MCMEM1 Register Bitmap
      • Table 6-28. MCATTx Register Bitmap
        • Figure 6-22. MCATT1 Register Bitmap
      • Table 6-29. MCIOx Register Bitmap
        • Figure 6-23. MCIO1 Register Bitmap
      • Table 6-30. Card Interface Command Assertion Code Table
    • 6.9.2 Expansion Memory Configuration Register (MECR)
      • Table 6-31. MECR Configuration Register Bitmap
    • 6.9.3 16-Bit PC Card Overview
      • Figure 6-24. 16-Bit PC Card Memory Map
      • Table 6-32. Common Memory Space Write Commands
      • Table 6-33. Common Memory Space Read Commands
      • Table 6-34. Attribute Memory Space Write Commands
      • Table 6-35. Attribute Memory Space Read Commands
      • Table 6-36. 16-Bit I/O Space Write Commands (nIOIS16 = 0)
      • Table 6-37. 16-Bit I/O Space Read Commands (nIOIS16 = 0)
      • Table 6-38. 8-Bit I/O Space Write Commands (nIOIS16 = 1)
      • Table 6-39. 8-Bit I/O Space Read Commands (nIOIS16 = 1)
    • 6.9.4 External Logic for 16-Bit PC Card Implementation
      • Figure 6-25. Expansion Card External Logic for a One-Socket Configuration
      • Figure 6-26. Expansion Card External Logic for a Two-Socket Configuration
    • 6.9.5 Expansion Card Interface Timing Diagrams and Parameters
      • Figure 6-27. 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access
      • Figure 6-28. 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device
  • 6.10 Companion Chip Interface
    • Figure 6-29. Alternate Bus Master Mode
    • Figure 6-30. Variable Latency IO
    • 6.10.1 Alternate Bus Master Mode
      • 1. The alternate master asserts MBREQ.
      • 2. The memory controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on.
      • 3. If the MDCNFG:SA1111x bit is enabled, the memory controller sends the SDRAMs an MRS command to change the SDRAM burst length to one. The burst length is changed to one for SA-1111 compatibility.
      • 4. The processor deasserts SDCKE<1> at time (t).
      • 5. The processor three-states SDRAM outputs at time (t + 1 MEMCLK).
      • 6. The processor asserts MBGNT at time (t + 2 MEMCLKS).
      • 7. The Alternate master drives SDRAM outputs before time (t + 3 MEMCLKS).
      • 8. The processor asserts SDCKE<1> at time (t + 4 MEMCLKS).
      • 1. The alternate master deasserts MBREQ.
      • 2. The processor deasserts SDCKE<1> at time (t).
      • 3. The processor deasserts MBGNT at time (t + 1 MEMCLK).
      • 4. The alternate master three-states SDRAM outputs prior to time (t + 2 MEMCLKS).
      • 5. The processor drives SDRAM outputs at time (t + 3 MEMCLKS).
      • 6. The processor asserts SDCKE<1> at time (t + 4 MEMCLKS).
      • 7. The memory controller performs an SDRAM refresh if SDRAM clocks and clock enable are turned on.
      • 8. The memory controller sends an MRS command to the SDRAMs if the MDCNFG:SA1111x bit is enabled. This changes the SDRAM burst length back to four.
      • 6.10.1.1 GPIO Reset
      • 6.10.1.2 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Disabled
        • Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is asserted.
      • 6.10.1.3 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Enabled
        • Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is asserted.
  • 6.11 Options and Settings for Boot Memory
    • 6.11.1 Alternate Booting
    • 6.11.2 Boot Time Defaults
      • 6.11.2.1 BOOT_DEF Read-Only Register (BOOT_DEF)
        • Table 6-40. BOOT_DEF Register Bitmap
      • 6.11.2.2 Boot-Time Configurations
        • Figure 6-31. Asynchronous Boot Time Configurations and Register Defaults
        • Figure 6-32. SMROM Boot Time Configurations and Register Defaults
        • Figure 6-33. SMROM Boot Time Configurations and Register Defaults (Continued)
    • 6.11.3 Memory Interface Reset and Initialization
      • Table 6-41. Memory Controller Pin Reset Values
  • 6.12 Hardware, Watchdog, or Sleep Reset Operation
    • 1. After hardware reset, complete a power-on wait period of 200 ms, which allows the internal clocks that generate SDCLK to stab...
    • a. Write MSC0, MSC1, MSC2
    • b. Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1
    • c. Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must contain a valid value. Deassert MDREFR:KxFREE.
    • 2. In systems that contain synchronous static memory, write to the SXCNFG to configure all appropriate bits, including the enabl...
    • a. Write SXCNFG (with enable bits asserted).
    • b. Write to SXMRS to trigger an MRS command to all enabled banks of synchronous static memory.
    • c. SXLCR must only be written when it is required by the SDRAM-like synchronous flash device for command encoding.
    • 3. In systems that contain SDRAM, transition the SDRAM controller through this state sequence:
    • a. self-refresh and clock-stop
    • b. self-refresh
    • c. power-down
    • d. PWRDNX
    • e. NOP
    • 4. The SDRAM clock run and enable bits (MDREFR:K1RUN, K2RUN, and E1PIN), described in Section 6.6.3. MDREFR:SLFRSH must not be asserted.
    • a. Write MDREFR:K1RUN , K2RUN (self-refresh and clock-stop -> self-refresh). Configure MDREFR:K1DB2,K2DB2.
    • b. Write MDREFR:SLFRSH (self-refresh -> power-down).
    • c. Write MDREFR:E1PIN (power-down -> PWRDNX).
    • d. a write is not required for this state transition (PWRDNX -> NOP).
    • e. Configure, but do not enable, each SDRAM partition pair.
    • f. Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to ‘0’.
    • 5. For systems that contain SDRAM, wait a specified NOP power-up waiting period required by the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition
    • 6. Ensure the Data Cache bit (DCACHE) is disabled. If this bit is enabled, the refreshes triggered by the next step may not pass through to the Memory Controller properly.
    • 7. On a hardware reset in systems that contain SDRAM, trigger the specified number (typically eight) of refresh cycles by attemp...
    • 8. Re-enable the DCACHE bit if it is disabled.
    • 9. In systems that contain SDRAM, enable SDRAM partitions by setting MDCNFG:DE3:2,DE1:0.
    • 10. In systems that contain SDRAM, write the MDMRS register to trigger an MRS command to all enabled banks of SDRAM. For each SD...
    • 11. Optionally, in systems that contain SDRAM or synchronous static memory, enable auto- power-down by setting MDREFR:APD.
  • 6.13 General Purpose Input/Output Reset Procedure
    • 1. The SDRAM refresh time is chosen by taking the specified refresh time, typically 64 ms, and subtracting the GPIO reset time (...
    • 2. In the boot code, determine the type of reset. If the reset was a GPIO reset, then refresh all the SDRAM rows. Refreshing all the SDRAM rows preserves their value in case GPIO reset occurs again.
    • 3. After all the SDRAM rows have been refreshed, enable GPIO reset.
• Liquid Crystal Display Controller 7
  • 7.1 Overview
    • 7.1.1 Features
      • Figure 7-1. LCD Controller Block Diagram
    • 7.1.2 Pin Descriptions
      • Table 7-1. Pin Descriptions
  • 7.2 Liquid Crystal Display Controller Operation
    • 7.2.1 Enabling the Controller
    • 7.2.2 Disabling the Controller
    • 7.2.3 Resetting the Controller
  • 7.3 Detailed Module Descriptions
    • 7.3.1 Input FIFOs
    • 7.3.2 Lookup Palette
    • 7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering
      • Figure 7-2. Temporal Dithering Concept - Single Color
      • Figure 7-3. Compare Range for TMED
        • 1. The new CV is sent through the color offset adjuster, where it is used as a lookup into the matrix selected by TCR[COAM].
        • 2. Either the 8-bit output of the chosen matrix or 00h, as selected by TCR[COAE], is added to the appropriate color’s seed register value in register TRGBR to form an offset.
        • 3. This offset is added to the result of the multiplication of the frame number and the CV to form the algorithm’s lower boundary (only the lower 8 bits are used).
        • 4. The CV is added to the lower boundary to obtain the upper boundary.
        • 5. Row (line) and column (pixel) counters are combined with beat suppression (offset) values in the pixel number adjuster and address generator to form yet another address for a matrix lookup.
        • 6. The output of the chosen matrix is compared to the lower and upper boundaries in the data generator.
        • 7. If the matrix output is between these boundaries or the original pixel value is 254 or 255, then the data output to the panel is one. In all other cases, it is zero.
      • Figure 7-4. TMED Block Diagram
    • 7.3.4 Output FIFOs
    • 7.3.5 Liquid Crystal Display Controller Pin Usage
      • 7.3.5.1 Passive-Display Timing
      • 7.3.5.2 Active-Display Timing
      • 7.3.5.3 Pixel Data Pins (L_DDx)
    • 7.3.6 Direct Memory Access
  • 7.4 Liquid Crystal Display External Palette and Frame Buffers
    • 7.4.1 External-Palette Buffer
      • Figure 7-5. Palette-Buffer Format
    • 7.4.2 External-Frame Buffer
      • Figure 7-6. 1-Bit Per Pixel Data Memory Organization
      • Figure 7-7. 2-Bits Per Pixel Data Memory Organization
      • Figure 7-8. 4-Bits Per Pixel Data Memory Organization
      • Figure 7-9. 8-Bits Per Pixel Data Memory Organization
      • Figure 7-10. 16-Bits Per Pixel Data Memory Organization - Passive Mode
      • Note: For passive 16 bits per pixel operation, the Raw Pixel Data must be organized as shown above.
        • Figure 7-11. 16-Bits Per Pixel Data Memory Organization - Active Mode
      • Note: For active 16-bits per pixel operation, the raw pixel data is sent directly to the LCD panel pins and must be in the format required by the LCD panel.
      • Note: There are two special conditions: 8 bits per pixel monochrome screens with double-pixel-data mode and 8- or 16-bits per pixel passive color screens require a multiple of 8 pixels for each line.
  • 7.5 Functional Timing
    • Figure 7-12. Passive Mode Start-of-Frame Timing
    • Figure 7-13. Passive Mode End-of-Frame Timing
    • Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing
    • Figure 7-15. Active Mode Timing
    • Figure 7-16. Active Mode Pixel Clock and Data Pin Timing
  • 7.6 Liquid Crystal Display Register Descriptions
    • 7.6.1 LCD Controller Control Register 0 (LCCR0)
      • Table 7-2. LCD Controller Control Register 0 (Sheet 1 of 3)
      • 7.6.1.1 LCD Output Fifo Underrun Mask (OUM)
      • 7.6.1.2 Branch Mask (BM)
      • 7.6.1.3 Palette DMA Request Delay (PDD)
      • 7.6.1.4 LCD Quick Disable Interrupt Mask (QDM)
      • 7.6.1.5 LCD Disable (DIS)
      • 7.6.1.6 Double-Pixel Data (DPD) Pin Mode
        • Note: DPD does not affect dual-panel monochrome mode, any of the color modes, or active mode. Clear DPD in these modes.
      • 7.6.1.7 Passive/Active Display Select (PAS)
        • Figure 7-17. Frame Buffer/Palette Output to LCD Data Pins in Active Mode
      • 7.6.1.8 End of Frame Mask (EFM)
      • 7.6.1.9 Input Fifo Underrun Mask (IUM)
      • 7.6.1.10 Start Of Frame Mask (SFM)
      • 7.6.1.11 LCD Disable Done Interrupt Mask (LDM)
      • 7.6.1.12 Single-/Dual-Panel Select (SDS)
        • Note: SDS must be set to 0 in active mode (PAS=1).
        • Note: In passive color mode, the data pin ordering switches. Figure 7-18 on page 7-27 shows the LCD data pin pixel ordering.
        • Table 7-3. LCD Controller Data Pin Utilization
          • Figure 7-18. LCD Data-Pin Pixel Ordering
      • 7.6.1.13 Color/Monochrome Select (CMS)
      • 7.6.1.14 LCD Enable (ENB)
    • 7.6.2 LCD Controller Control Register 1 (LCCR1)
      • Table 7-4. LCD Controller Control Register 1 (Sheet 1 of 2)
      • 7.6.2.1 Beginning-of-Line Pixel Clock Wait Count (BLW)
      • 7.6.2.2 End-of-Line Pixel Clock Wait Count (ELW)
      • 7.6.2.3 Horizontal Sync Pulse Width (HSW)
        • Note: For this section, the term “pulse width” refers to the time which L_LCLK is asserted, rather than the time for a cycle of the line clock to occur.
      • 7.6.2.4 Pixels Per Line (PPL)
    • 7.6.3 LCD Controller Control Register 2 (LCCR2)
      • Table 7-5. LCD Controller Control Register 2
      • 7.6.3.1 Beginning-of-Frame Line Clock Wait Count (BFW)
      • 7.6.3.2 End-of-Frame Line Clock Wait Count (EFW)
      • 7.6.3.3 Vertical Sync Pulse Width (VSW)
      • 7.6.3.4 Lines Per Panel (LPP)
    • 7.6.4 LCD Controller Control Register 3 (LCCR3)
      • Table 7-6. LCD Controller Control Register 3 (Sheet 1 of 2)
      • 7.6.4.1 Double Pixel Clock (DPC)
      • 7.6.4.2 Bits Per Pixel (BPP)
      • 7.6.4.3 Output Enable Polarity (OEP)
      • 7.6.4.4 Pixel Clock Polarity (PCP)
      • 7.6.4.5 Horizontal Sync Polarity (HSP)
      • 7.6.4.6 Vertical Sync Polarity (VSP)
      • 7.6.4.7 AC Bias Pin Transitions Per Interrupt (API)
      • 7.6.4.8 AC Bias Pin Frequency (ACB)
      • 7.6.4.9 Pixel Clock Divider (PCD)
    • 7.6.5 LCD Controller DMA
      • 7.6.5.1 Frame Descriptors
        • Note: If only one frame buffer is used in external memory, the FDADRx field (word[0] of the frame descriptor) must point back to itself.
      • 7.6.5.2 LCD DMA Frame Descriptor Address Registers (FDADRx)
        • Table 7-7. LCD DMA Frame Descriptor Address Registers
      • 7.6.5.3 LCD DMA Frame Source Address Registers (FSADRx)
        • Table 7-8. LCD DMA Frame Source Address Registers
      • 7.6.5.4 LCD DMA Frame ID Registers (FIDRx)
        • Table 7-9. LCD Frame ID Registers
      • 7.6.5.5 LCD DMA Command Registers (LDCMDx)
        • Table 7-10. LCD DMA Command Registers
          • Note: Never set the PAL bit in LDCMD1, since the palette is always loaded with Channel 0.
          • Note: Use a separate descriptor to fetch the frame data.
    • 7.6.6 LCD DMA Frame Branch Registers (FBRx)
      • Note: In dual-panel mode, write to both FBR0 and FBR1 in order to branch properly.
      • Table 7-11. LCD DMA Frame Branch Registers (FBRx)
    • 7.6.7 LCD Controller Status Register (LCSR)
      • Table 7-12. LCD Controller Status Register (Sheet 1 of 2)
      • 7.6.7.1 Subsequent Interrupt Status (SINT)
        • Note: If a branched-to descriptor has SOF set, both the SOF and branch interrupts are signalled at the same time, and SINT is not set.
      • 7.6.7.2 Branch Status (BS)
      • 7.6.7.3 End Of Frame Status (EOF)
      • 7.6.7.4 LCD Quick Disable Status (QD)
      • 7.6.7.5 Output FIFO Underrun Status (OU)
      • 7.6.7.6 Input FIFO Underrun Upper Panel Status (IUU)
      • 7.6.7.7 Input FIFO Underrun Lower Panel Status (IUL)
      • 7.6.7.8 AC Bias Count Status (ABC)
      • 7.6.7.9 Bus Error Status (BER)
      • 7.6.7.10 Start Of Frame Status (SOF)
      • 7.6.7.11 LCD Disable Done Status (LDD)
    • 7.6.8 LCD Controller Interrupt ID Register (LIIDR)
      • Table 7-13. LCD Controller Interrupt ID Register
    • 7.6.9 TMED RGB Seed Register
      • Table 7-14. TMED RGB Seed Register
    • 7.6.10 TMED Control Register (TCR)
      • Table 7-15. TMED Control Register (Sheet 1 of 2)
      • 7.6.10.1 TMED Energy Distribution Select (TED)
      • 7.6.10.2 TMED Horizontal Beat Suppression (THBS)
      • 7.6.10.3 TMED Vertical Beat Suppression (TVBS)
      • 7.6.10.4 TMED Frame Number Adjuster Enable (FNAME)
      • 7.6.10.5 TMED Color Offset Adjuster Enable (COAE)
      • 7.6.10.6 TMED Frame Number Adjuster Matrix (FNAM)
      • 7.6.10.7 TMED Color Offset Adjuster Matrix (COAM)
    • 7.6.11 LCD Controller Register Summary
      • Table 7-16. LCD Controller Register Locations (Sheet 1 of 2)
• Synchronous Serial Port Controller 8
  • 8.1 Overview
  • 8.2 Signal Description
    • 8.2.1 External Interface to Synchronous Serial Peripherals
      • Table 8-1. External Interface to Codec
  • 8.3 Functional Description
    • 8.3.1 Data Transfer
  • 8.4 Data Formats
    • 8.4.1 Serial Data Formats for Transfer to/from Peripherals
      • 8.4.1.1 SSP Format Details
        • Figure 8-1. Texas Instruments’ Synchronous Serial Frame* Format
      • 8.4.1.2 SPI Format Details
        • Figure 8-2. Motorola SPI* Frame Format
      • 8.4.1.3 Microwire Format Details
        • Figure 8-3. National Microwire* Frame Format
    • 8.4.2 Parallel Data Formats for FIFO Storage
  • 8.5 FIFO Operation and Data Transfers
    • 8.5.1 Using Programmed I/O Data Transfers
    • 8.5.2 Using DMA Data Transfers
      • 1. Program the transmit/receive byte count (buffer length) and burst size.
      • 2. Program the DMA request to channel map register for SSP.
      • 3. Set the run bit in the DMA control register.
      • 4. Set the desired values in the SSP control registers.
      • 5. Enable the SSP by setting the SSE bit in the SSP Control Register 0 (see Section 8.7.1).
      • 6. Wait for both the DMA transmit and receive interrupt requests.
      • Note: If the transmit/receive byte count is not a multiple of the transfer burst size, the user must check the SSP Status Register (see Section 8.7.4) to determine if any data remains in the receive FIFO.
  • 8.6 Baud Rate Generation
  • 8.7 SSP Serial Port Registers
    • 8.7.1 SSP Control Register 0 (SSCR0)
      • Table 8-2. SSP Control Register 0 (SSCR0) Bitmap and Bit Definitions
      • 8.7.1.1 Data Size Select (DSS)
      • 8.7.1.2 Frame Format (FRF)
      • 8.7.1.3 External Clock Select (ECS)
        • Note: Disable the SSPC by setting the SSPC Enable (SSE) to a 0 before setting the ECS bit to a 1. Set the ECS bit to 1 either before the SSE is set to 1 or at the same time.
      • 8.7.1.4 Synchronous Serial Port Enable (SSE)
        • Note: After reset or after the SSCR0[SSE] is cleared, ensure that the SSCR1 and SSSR registers are properly reconfigured or rese...
      • 8.7.1.5 Serial Clock Rate (SCR)
    • 8.7.2 SSP Control Register 1 (SSCR1)
      • Table 8-3. SSP Control Register 1 (SSCR1) Bitmap and Definitions (Sheet 1 of 2)
      • 8.7.2.1 Receive FIFO Interrupt Enable (RIE)
      • 8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
      • 8.7.2.3 Loop Back Mode (LBM)
        • Note: Loop back mode cannot be used with Microwire frame format.
      • 8.7.2.4 Serial Clock Polarity (SPO)
        • Note: The SPO bit is ignored for all data frame formats except for the Motorola SPI format (FRF=00).
      • 8.7.2.5 Serial Clock Phase (SPH)
        • Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming
      • 8.7.2.6 Microwire Transmit Data Size (MWDS)
      • 8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT)
      • 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
        • Table 8-4. TFT and RFT Values for DMA Servicing
    • 8.7.3 SSP Data Register (SSDR)
      • Note: Both FIFOs are cleared when the SSPC is reset or a zero is written to the SSCR0[SSE] bit.
      • Table 8-5. SSP Data Register (SSDR) Bitmap and Definitions
    • 8.7.4 SSP Status Register (SSSR)
      • Table 8-6. SSP Status Register (SSSR) Bitmap and Bit Definitions
      • 8.7.4.1 Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible)
      • 8.7.4.2 Receive FIFO Not Empty Flag (RNE) (read-only, non-interruptible)
      • 8.7.4.3 SSP Busy Flag (BSY) (read-only, non-interruptible)
      • 8.7.4.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)
      • 8.7.4.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)
      • 8.7.4.6 Receiver Overrun Status (ROR) (read/write, non-maskable interrupt)
      • 8.7.4.7 Transmit FIFO Level
      • 8.7.4.8 Receive FIFO Level
    • 8.7.5 SSP Register Address Map
      • Table 8-7. SSP Register Address Map
• Inter-Integrated Circuit Bus Interface Unit 9
  • This chapter describes the Inter-Integrated Circuit (I2C) bus interface unit, including the operation modes and setup for the Intel® PXA26x Processor Family.
  • 9.1 Overview
    • The I2C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface. The SDA data pin is used for i...
    • The I2C unit enables the processor to communicate with I2C peripherals and microcontrollers for system management functions. The...
    • The I2C unit is a peripheral device that resides on the processor internal bus. Data is transmitted to and received from the I2C...
    • Note: The I2C unit does not support the hardware general call, 10-bit addressing, or CBUS compatibility.
  • 9.2 Signal Description
    • The I2C unit signals are SDA and SCL. Table 9-1 describes each signal’s function.
    • Table 9-1. MMC Signal Description
  • 9.3 Functional Description
    • The I2C bus defines a serial protocol for passing information between agents on the I2C bus using a two pin interface that consi...
    • Table 9-2. I2C Bus Definitions
      • For example, when the processor I2C unit acts as a master on the bus, it addresses an EEPROM as a slave to receive data (see Fig...
      • Figure 9-1. I2C Bus Configuration Example
        • The I2C bus allows for a multi-master system, which means more than one device can initiate data transfers at the same time. To ...
        • The I2C bus serial operation uses an open-drain wired-AND bus structure, which allows multiple devices to drive the bus lines an...
        • I2C transactions are either initiated by the processor as a master or received by the processor as a slave. Both conditions may result in reads, writes, or both to the I2C bus.
    • 9.3.1 Operational Blocks
      • The I2C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to notify the CPU that there is a...
      • The I2C unit initiates an interrupt to the processor when a buffer is full, a buffer is empty, the I2C unit slave address is det...
      • The 8-bit I2C Data Buffer Register (IDBR) is loaded with a byte of data from the shift register interface to the I2C bus when receiving data and from the processor internal bus when writing data. The serial shift register is not user accessible.
      • The I2C Control Register (ICR) and the I2C Status Register (ISR) are located in the I2C memory- mapped address space. The registers and their functions are defined in Section 9.9, “Register Definitions”.
      • The I2C unit supports a fast mode operation of 400 Kbits/sec and a standard mode of 100 Kbits/sec. Refer to the I2C-Bus Specification for details.
    • 9.3.2 Inter-Integrated Circuit Bus Interface Modes
      • The I2C unit can accomplish a transfer in different operation modes. Table 9-3 summarizes the different modes.
      • Table 9-3. Modes of Operation
        • While the I2C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the bus and receive any slave addresses intended for the processor.
        • When the I2C unit receives an address that matches the 7-bit address found in the I2C Slave Address Register (ISAR) or the gener...
        • When the I2C unit initiates a read or write on the I2C bus, it transitions from the default slave- receive mode to the master-tr...
    • 9.3.3 Start and Stop Bus States
      • The I2C bus specification defines a transaction START, used at the beginning of a transfer, and a transaction STOP bus state, us...
      • The I2C unit uses the ICR[START] and ICR[STOP] bits to:
      • Table 9-4 defines the START and STOP bits in the ICR.
      • Table 9-4. START and STOP Bit Definitions
        • Figure 9-2 shows the relationship between the SDA and SCL lines for START and STOP conditions.
        • Figure 9-2. Start and Stop Conditions
      • 9.3.3.1 START Condition
        • The START condition (ICR[START]=1, ICR[STOP]=0) initiates a master transaction or repeated START. Before it sets the START ICR b...
        • The START condition is not cleared by the I2C unit. If the I2C loses arbitration while initiating a START, it may re-attempt the...
      • 9.3.3.2 No START or STOP Condition
        • Use the no START or STOP condition (ICR[START]=0, ICR[STOP]=0) in master-transmit mode while the I2C unit is transmitting multip...
        • After each byte transfer, including the ICR[ACKNAK] bit, the I2C unit holds the SCL line low to insert wait states until the ICR[TB] bit is set. This action notifies the I2C unit to release the SCL line and allow the next information transfer to proceed.
      • 9.3.3.3 STOP Condition
        • The STOP condition (ICR[START]=X, ICR[STOP]=1) terminates a data transfer. In master- transmit mode, the ICR[STOP] bit and the I...
        • Figure 9-3. START and STOP Conditions
  • 9.4 Inter-Integrated Circuit Bus Operation
    • The I2C unit transfers data in 1-byte increments and always follows this sequence:
      • 1. START
      • 2. 7-bit slave address
      • 3. R/nW Bit
      • 4. Acknowledge pulse
      • 5. 8 Bits of data
      • 6. ACK/NAK pulse
      • 7. Repeat of Steps 5 and 6 for required number of bytes
      • 8. Repeated START (Repeat Step 1) or STOP
    • 9.4.1 Serial Clock Line (SCL) Generation
      • When the I2C unit is in master-transmit or master-receive mode, it generates the I2C clock output. The SCL clock is generated by setting the ICR[FM] bit for either 100 KBit/sec or 400 Kbit/sec operation.
    • 9.4.2 Data and Addressing Management
      • The I2C Data Buffer Register (IDBR) and the I2C Slave Address Register (ISAR) manage data and slave addressing. The IDBR (see Se...
      • When the I2C unit is in master- or slave-transmit mode:
      • When the I2C unit is in master- or slave-receive mode:
      • 9.4.2.1 Addressing a Slave Device
        • As a master device, the I2C unit must compose and send the first byte of a transaction. This byte consists of the slave address ...
        • Figure 9-4. Data Format of First Byte in Master Transaction
          • The first byte transmission must be followed by an ACK pulse from the addressed slave. When the transaction is a write, the I2C ...
          • When the I2C unit is enabled and idle, it remains in slave-receive mode and monitors the I2C bus for a START signal. When it det...
    • 9.4.3 Inter-Integrated Circuit Acknowledge
      • Every I2C byte transfer must be accompanied by an acknowledge pulse that the master- or slave- receiver must generate. The transmitter must release the SDA line for the receiver to transmit the acknowledge pulse (see Figure 9-5).
      • Figure 9-5. Acknowledge on the I2C Bus
        • In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse, the SDA line remains high. T...
        • In master-receive mode, the I2C unit sends a negative acknowledge (NAK) to signal the slave- transmitter to stop sending data. T...
        • In slave mode, the I2C unit automatically acknowledges its own slave address, independent of the value in the ICR[ACKNAK] bit. I...
        • In slave-transmit mode, the I2C unit receives a NAK from the master to indicate the last byte has been transferred. The master then sends a STOP or repeated START. The ISR[UB] bit remains set until a STOP or repeated START is received.
    • 9.4.4 Arbitration
      • The I2C bus’ multi-master capabilities require I2C bus arbitration. Arbitration takes place when two or more masters generate a START condition in the minimum hold time.
      • Arbitration can take a long time. If the address bit and the R/nW are the same, the arbitration scheme considers the data. Becau...
      • 9.4.4.1 SCL Arbitration
        • Each master on the I2C bus generates its own clock on the SCL line for data transfers. As a result, clocks with different freque...
        • Clock synchronization is through the wired-AND connection of the I2C interfaces to the SCL line. When a master’s clock changes f...
        • Figure 9-6. Clock Synchronization During the Arbitration Procedure
          • The first master to complete its high period pulls the SCL line low.
      • 9.4.4.2 SDA Arbitration
        • Arbitration on the SDA line can continue for a long time because it starts with the address and R/ nW bits and continues through...
        • Figure 9-7. Arbitration Procedure of Two Masters
          • If the I2C unit loses arbitration as the address bits are transferred and it is not addressed by the address bits, the I2C unit ...
          • If the I2C unit loses arbitration because another bus master addresses the processor as a slave device, the I2C unit switches to...
        • Note: Software must prevent the I2C unit from starting a transaction to its own slave address because such a transaction puts the I2C unit in an indeterminate state.
          • Arbitration has boundary conditions in case an arbitration process is interrupted by a repeated START or STOP condition transmit...
          • These situations occur if different masters write identical data to the same target slave simultaneously and arbitration cannot be resolved after the first data byte transfer.
        • Note: Software ensures that arbitration is resolved quickly. For example, software can ensure that masters send unique data by r...
    • 9.4.5 Master Operations
      • When software initiates a read or write on the I2C bus, the I2C unit transitions from the default slave-receive mode to master-t...
      • The CPU writes to the ICR register to initiate a master transaction. Data is read and written from the I2C unit through the memory-mapped registers. Table 9-5 describes the I2C unit’s responsibilities as a master device.
      • Table 9-5. Master Transactions (Sheet 1 of 2)
        • When the CPU needs to read data, the I2C unit transitions from slave-receive mode to master- transmit mode to transmit the start...
        • Figure 9-8. Master-Receiver Read from Slave-Transmitter
        • Figure 9-9. Master-Receiver Read from Slave-Transmitter / Repeated Start / Master- Transmitter Write to Slave-Receiver
        • Figure 9-10. A Complete Data Transfer
    • 9.4.6 Slave Operations
      • Table 9-6 describes how the I2C unit operates as a slave device.
      • Table 9-6. Slave Transactions
        • Figure 9-11 through Figure 9-13 are examples of I2C transactions and show the relationships between master and slave devices.
        • Figure 9-11. Master-Transmitter Write to Slave-Receiver
        • Figure 9-12. Master-Receiver Read to Slave-Transmitter
        • Figure 9-13. Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to Slave-Receiver
    • 9.4.7 General Call Address
      • A general call address is a transaction with a slave address of 0x00. When a device requires the data from a general call addres...
      • The I2C unit supports sending and receiving general call address transfers on the I2C bus. When software sends a general call me...
      • If the I2C unit acts as a slave and receives a general call address while the ICR[GCD] bit is clear, it:
      • If the I2C unit receives a general call address and the ICR[GCD] bit is set, it ignores the general call address.
      • Figure 9-14. General Call Address
      • Table 9-7. General Call Address Second Byte Definitions
        • Software must ensure that the I2C unit is not busy before it asserts a reset. Software must also ensure that the I2C bus is idle...
        • When B=1, the sequence is a hardware general call and is not supported by the I2C unit. Refer to the I2C-Bus Specification for information on hardware general calls.
        • I2C 10-bit addresses and CBUS compatibility are not supported.
  • 9.5 Slave Mode Programming Examples
    • The following sub-sections describe slave mode programming.
    • 9.5.1 Initialize Unit
      • To initialize the unit:
        • 1. Set the slave address in the ISAR.
        • 2. Enable desired interrupts in the ICR.
        • 3. Set the ICR[IUE] bit to enable the I2C unit.
    • 9.5.2 Write n Bytes as a Slave
      • To write n bytes as a slave:
        • 1. When a Slave Address Detected interrupt occurs. Read ISR: slave address detected (1), unit busy (1), R/nW bit (1), ACK/NAK (0)
        • 2. Write a 1 to the ISR[SAD] bit to clear the interrupt.
        • 3. Return from interrupt.
        • 4. Load data byte to transfer in the IDBR.
        • 5. Set ICR[TB] bit.
        • 6. When a IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), ACK/NAK (0), R/nW bit (0)
        • 7. Load data byte to transfer in the IDBR.
        • 8. Set the ICR[TB] bit.
        • 9. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 10. Return from interrupt.
        • 11. Repeat steps 6 to 10 for n-1 times. If, at any time, the slave does not have data, the I2C unit keeps SCL low until data is available.
        • 12. When a IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), ACK/NAK (1), R/nW bit (0)
        • 13. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 14. Return from interrupt
        • 15. When slave stop detected interrupt occurs. Read ISR: unit busy (0), slave STOP detected (1)
        • 16. Write a 1 to the ISR[SSD] bit to clear interrupt.
    • 9.5.3 Read n Bytes as a Slave
      • To read n bytes as a slave:
        • 1. When a slave address detected interrupt occurs. Read ISR: slave address detected (1), unit busy (1), R/nW bit (0)
        • 2. Write a 1 to the ISR[SAD] bit to clear the interrupt.
        • 3. Return from interrupt.
        • 4. Set ICR[TB] bit to initiate the transfer.
        • 5. When an IDBR receive full interrupt occurs. Read ISR: IDBR receive full (1), ACK/NAK (0), R/nW bit (0)
        • 6. Read IDBR to get the received byte.
        • 7. Write a 1 to the ISR[IRF] bit to clear interrupt.
        • 8. Return from interrupt.
        • 9. Repeat steps 4 to 8 for n-1 times. Once the IDBR is full, the I2C unit will keep SCL low until the data is read.
        • 10. Set ICR[TB] bit to release I2C bus and allow next transfer.
        • 11. When a slave stop detected interrupt occurs. Read ISR: unit busy (0), slave STOP detected (1)
        • 12. Write a 1 to the ISR[SSD] bit to clear interrupt.
  • 9.6 Master Programming Examples
    • The following sub-sections describe master programming.
    • 9.6.1 Initialize Unit
      • To initialize the unit:
        • 1. Set the slave address in the ISAR.
        • 2. Enable desired interrupts in the ICR. Do not enable arbitration loss detected interrupt
        • 3. Set the ICR[IUE] and ICR[SCLE] bits to enable the I2C unit and SCL.
    • 9.6.2 Write 1 Byte as a Master
      • To write 1 byte as a master:
        • 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 0 for a write.
        • 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
        • 3. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0)
        • 4. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 5. Write a 1 to the ISR[ALD] bit if set. If the master loses arbitration, it performs an address retry when the bus becomes free. The arbitration loss detected interrupt is disabled to allow the address retry.
        • 6. Load data byte to be transferred in the IDBR.
        • 7. Initiate the write. Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[TB]
        • 8. When an IDBR transmit empty interrupt occurs (unit is sending STOP). Read ISR: IDBR transmit empty (1), unit busy (x), R/nW bit (0)
        • 9. Write a 1 to the ISR[ITE] bit to clear the interrupt.
        • 10. Clear ICR[STOP] bit.
    • 9.6.3 Read 1 Byte as a Master
      • To read 1 byte as a master:
        • 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
        • 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
        • 3. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
        • 4. Write a 1 to the ISR[ITE] bit to clear the interrupt.
        • 5. Initiate the read. Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]
        • 6. When an IDBR receive full interrupt occurs (unit is sending STOP). Read ISR: IDBR receive full (1), unit busy (x), R/nW bit (1), ACK/NAK bit (1)
        • 7. Write a 1 to the ISR[IRF] bit to clear the interrupt.
        • 8. Read IDBR data.
        • 9. Clear ICR[STOP] and ICR[ACKNAK] bits
    • 9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master
      • To write 2 bytes and execute a repeated start to read 1 byte as a master:
        • 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 0 for a write.
        • 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
        • 3. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0)
        • 4. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 5. Load data byte to be transferred in the IDBR.
        • 6. Initiate the write. Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], set ICR[TB]
        • 7. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0)
        • 8. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 9. Repeat steps 5-8 one time.
        • 10. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
        • 11. Send repeated start as a master. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
        • 12. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
        • 13. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 14. Initiate the read. Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]
        • 15. When an IDBR receive full interrupt occurs (unit is sending stop). Read ISR: IDBR receive full (1), unit busy (x), R/nW bit (1), ACK/NAK bit (1)
        • 16. Write a 1 to the ISR[IRF] bit to clear the interrupt.
        • 17. Read IDBR data.
        • 18. Clear ICR[STOP] and ICR[ACKNAK] bits
    • 9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort
      • To read 2 bytes as a master and send a STOP using the abort:
        • 1. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
        • 2. Initiate the write. Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]
        • 3. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (1)
        • 4. Write a 1 to the ISR[ITE] bit to clear interrupt.
        • 5. Initiate the read Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], clear ICR[ACKNAK], set ICR[TB]
        • 6. When an IDBR receive full interrupt occurs. Read ISR: IDBR receive full (1), unit busy (1), R/nW bit (1), ACK/NAK bit (0)
        • 7. Write a 1 to the ISR[IRF] bit to clear the interrupt.
        • 8. Read IDBR data.
        • 9. Clear ICR[STOP] and ICR[ACKNAK] bits
        • 10. Initiate the read. Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB] ICR[STOP] is not set because STOP or repeated start will be decided on the byte read.
        • 11. When an IDBR receive full interrupt occurs. Read ISR: IDBR receive full (1), unit busy (1), R/nW bit (1), ACK/NAK bit (1)
        • 12. Write a 1 to the ISR[IRF] bit to clear the interrupt.
        • 13. Read IDBR data.
        • 14. Initiate STOP abort condition (STOP with no data transfer). Set ICR[MA]
      • Note: If a NAK is not sent in step 11, the next transaction must involve another data byte read.
  • 9.7 Glitch Suppression Logic
    • The I2C unit has built-in glitch suppression logic that suppresses glitches of 60ns or less. This is within the 50ns glitch suppression specification.
  • 9.8 Reset Conditions
    • Software must ensure that the I2C unit is not busy before it asserts a reset. Software must also ensure that the I2C bus is idle...
    • When the ICR[UR] bit is set, the I2C unit resets but the associated I2C MMRs remain intact. When resetting the I2C unit with the ICR’s unit reset, use the following guidelines:
      • 1. Set the reset bit in the ICR register and clear the remainder of the register.
      • 2. Clear the ISR register.
      • 3. Clear reset in the ICR.
  • 9.9 Register Definitions
    • The registers in Table 9-8 are associated with the I2C unit and are located in the processor peripheral memory-mapped address space.
    • Table 9-8. I2C Register Definitions
    • 9.9.1 I2C Bus Monitor Register- IBMR
      • The I2C Bus Monitor Register (IBMR) tracks the status of the SCL and SDA pins. The values of these pins are recorded in this read-only IBMR so software can determine when the I2C bus is hung and the I2C unit must be reset.
      • Table 9-9. I2C Bus Monitor Register - IBMR
    • 9.9.2 I2C Data Buffer Register- IDBR
      • The processor uses the I2C Data Buffer Register to transmit and receive data from the I2C bus. The IDBR is accessed by the progr...
      • When the I2C unit is in transmit mode (master or slave), the processor writes data to the IDBR over the internal bus. The proces...
      • When the I2C unit is in receive mode (master or slave), the processor reads IDBR data over the internal bus. The processor reads...
      • Table 9-10. I2C Data Buffer Register - IDBR (Sheet 1 of 2)
    • 9.9.3 I2C Control Register- ICR
      • The processor uses the bits in the I2C Control Register (ICR) to control the I2C unit.
      • Table 9-11. I2C Control Register - ICR (Sheet 1 of 3)
    • 9.9.4 I2C Status Register
      • The ISR signals I2C interrupts to the processor interrupt controller. Software can use the ISR bits to check the status of the I2C unit and bus. ISR bits (bits 9-5) are updated after the ACK/NAK bit is completed on the I2C bus.
      • The ISR also clears the following interrupts signalled from the I2C unit:
      • Table 9-12. I2C Status Register - ISR (Sheet 1 of 2)
    • 9.9.5 I2C Slave Address Register- ISAR
      • The ISAR (see Table 9-13) defines the I2C unit’s 7-bit slave address. In slave-receive mode, the processor responds when the 7-b...
      • Table 9-13. I2C Slave Address Register - ISAR
• Universal Asynchronous Receiver/ Transmitter 10
  • 10.1 Feature List
  • 10.2 Overview
    • 10.2.1 Full Function UART
    • 10.2.2 Bluetooth UART
    • 10.2.3 Standard UART
    • 10.2.4 Compatibility with 16550
  • 10.3 Signal Descriptions
    • Table 10-1. UART Signal Descriptions (Sheet 1 of 2)
  • 10.4 UART Operational Description
    • Figure 10-1. Example UART Data Frame
    • Figure 10-2. Example NRZ Bit Encoding (0b0100 1011)
    • 10.4.1 Reset
    • 10.4.2 Internal Register Descriptions
      • Table 10-2. UART Register Addresses as Offsets of a Base
      • 10.4.2.1 Receive Buffer Register (RBR)
        • Table 10-3. Receive Buffer Register - RBR
      • 10.4.2.2 Transmit Holding Register (THR)
        • Table 10-4. Transmit Holding Register - THR
      • 10.4.2.3 Divisor Latch Registers (DLL and DLH)
        • Table 10-5. Divisor Latch Low Register - DLL
        • Table 10-6. Divisor Latch High Register - DLH
      • 10.4.2.4 Interrupt Enable Register (IER)
        • Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if an error interrupt exist...
        • Table 10-7. Interrupt Enable Register - IER (Sheet 1 of 2)
          • Note: To ensure that the DMA controller and programmed I/O do not access the same FIFO, software must not set the DMAE while the TIE or RAVIE bits are set to a 1.
      • 10.4.2.5 Interrupt Identification Register (IIR)
        • Table 10-8. Interrupt Conditions
        • Table 10-9. Interrupt Identification Register - IIR
        • Table 10-10. Interrupt Identification Register Decode
      • 10.4.2.6 FIFO Control Register (FCR)
        • Table 10-11. FIFO Control Register - FCR
      • 10.4.2.7 Line Control Register (LCR)
        • Table 10-12. Line Control Register - LCR (Sheet 1 of 2)
      • 10.4.2.8 Line Status Register (LSR)
        • Table 10-13. Line Status Register - LSR (Sheet 1 of 2)
      • 10.4.2.9 Modem Control Register (MCR)
        • Table 10-14. Modem Control Register - MCR (Sheet 1 of 2)
      • 10.4.2.10 Modem Status Register (MSR)
        • Note: When bit 0, 1, 2, or 3 is set, a modem status interrupt is generated if IER[MIE] is set.
        • Table 10-15. Modem Status Register - MSR
      • 10.4.2.11 Scratchpad Register (SPR)
        • Table 10-16. Scratch Pad Register - SPR
    • 10.4.3 FIFO Interrupt Mode Operation
      • 10.4.3.1 Receive Interrupt
      • 10.4.3.2 Character Timeout Indication Interrupt
      • 10.4.3.3 Transmit Interrupt
    • 10.4.4 FIFO Polled Mode Operation
    • 10.4.5 DMA Requests
      • Note: Do not program the channel to read more data than the FIFO trigger level.
      • Note: Ensure that the DMAC has finished previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO.
      • 10.4.5.1 Trailing Bytes in the Receive FIFO
        • 1. Wait for a character timeout indication interrupt. The character timeout indication interrupt must be enabled.
        • 2. Disable the receive DMA channel and wait for it to stop.
        • 3. Read one byte at a time. The FIFO is empty when LSR[DR] is cleared.
        • 4. Re-enable the receive DMA channel.
    • 10.4.6 Slow Infrared Asynchronous Interface
      • 10.4.6.1 Infrared Selection Register (ISR)
        • Table 10-17. Infrared Selection Register - ISR
      • 10.4.6.2 Operation
        • Figure 10-3. IR Transmit and Receive Example
        • Figure 10-4. XMODE Example
        • Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check t...
  • 10.5 Register Summary
    • Table 10-18. FFUART Register Addresses
    • Table 10-19. BTUART Register Locations
    • Table 10-20. STUART Register Locations
    • 10.5.1 UART Register Differences
      • Table 10-21. Flow Control Registers in BTUART and STUART
• Fast Infrared Communication Port 11
  • 11.1 Signal Description
    • Table 11-1. FICP Signal Description
  • 11.2 Fast Infrared Communications Port Operation
    • 11.2.1 Four-Position Pulse Modulation
      • Figure 11-1. 4PPM Modulation Encodings
      • Figure 11-2. 4PPM Modulation Example
    • 11.2.2 Frame Format
      • Figure 11-3. Frame Format for IrDA Transmission (4.0 Mbps)
    • 11.2.3 Address Field
    • 11.2.4 Control Field
    • 11.2.5 Data Field
    • 11.2.6 CRC Field
      • Note: Unlike the address, control, and data fields, the 32-bit inverted CRC value is transmitted and received most significant nibble first.
    • 11.2.7 Baud Rate Generation
    • 11.2.8 Receive Operation
    • 11.2.9 Transmit Operation
    • 11.2.10 Transmit and Receive FIFOs
    • 11.2.11 Trailing or Error Bytes in the Receive FIFO
  • 11.3 Fast Infrared Communications Port Register Descriptions
    • 11.3.1 FICP Control Register 0
      • Table 11-2. Fast Infrared Communication Port Control Register 0 (Sheet 1 of 2)
    • 11.3.2 FICP Control Register 1
      • Table 11-3. Fast Infrared Communication Port Control Register 1
    • 11.3.3 FICP Control Register 2
      • Table 11-4. Fast Infrared Communication Port Control Register 2 (Sheet 1 of 2)
    • 11.3.4 FICP Data Register
      • Table 11-5. Fast Infrared Communication Port Data Register
    • 11.3.5 FICP Status Register 0
      • Table 11-6. Fast Infrared Communication Port Status Register 0
    • 11.3.6 FICP Status Register 1
      • Table 11-7. Fast Infrared Communication Port Status Register 1
  • 11.4 Fast Infrared Communications Port Register Locations
    • Table 11-8. FICP Control, Data, and Status Register Locations
• Universal Serial Bus Device Controller 12
  • 12.1 Universal Serial Bus Overview
  • 12.2 Device Configuration
    • Table 12-1. Endpoint Configuration
  • 12.3 Universal Serial Bus Protocol
    • 12.3.1 Signalling Levels
      • Table 12-2. USB States
    • 12.3.2 Bit Encoding
      • Figure 12-1. NRZI Bit Encoding Example
    • 12.3.3 Field Formats
    • 12.3.4 Packet Formats
      • 12.3.4.1 Token Packet Type
        • Table 12-3. IN, OUT, and SETUP Token Packet Format
      • 12.3.4.2 Start of Frame Packet Type
        • Table 12-4. SOF Token Packet Format
      • 12.3.4.3 Data Packet Type
        • Table 12-5. Data Packet Format
      • 12.3.4.4 Handshake Packet Type
        • Table 12-6. Handshake Packet Format
    • 12.3.5 Transaction Formats
      • 12.3.5.1 Bulk Transaction Type
        • Table 12-7. Bulk Transaction Formats
      • 12.3.5.2 Isochronous Transaction Type
        • Table 12-8. Isochronous Transaction Formats
      • 12.3.5.3 Control Transaction Type
        • Table 12-9. Control Transaction Formats
      • 12.3.5.4 Interrupt Transaction Type
        • Table 12-10. Interrupt Transaction Formats
    • 12.3.6 UDC Device Requests
      • Table 12-11. Host Device Request Summary
    • 12.3.7 Configuration
  • 12.4 UDC Hardware Connection
    • 12.4.1 Self-Powered Device
      • Figure 12-2. Self-Powered Device
      • 12.4.1.1 When GPIOn and GPIOx are Different Pins
      • 12.4.1.2 When GPIOn and GPIOx are the Same Pin
    • 12.4.2 Bus-Powered Devices
  • 12.5 UDC Operation
    • 12.5.1 Case 1: EP0 Control Read
      • 1. When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track endpoints stages when software communicates with the host PC.
      • 2. The host PC sends a SETUP command.
      • 3. UDC generates an EP0 Interrupt.
      • 4. Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.
      • 5. Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.
      • 6. Software parses the command in the buffer and determines that it is a Control Read.
      • 7. Software starts to load the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE.
      • 8. After it reads and parses the data, software clears the UDCCS0[SA] and the UDCCS0[OPR] bits and sets the UDCCS0[IPR] bit, if ...
      • 9. Software clears the UDC interrupt bit and returns from the interrupt service routine.
      • 10. The host PC issues an IN packet, which the UDC sends data back to the host. After the host PC sends an ACK to the UDC, the UDC clears the UDDCS0[IPR] bit and generates an interrupt.
      • 11. Software enters the ISR routine and examines its internal state machine. It determines that it is in the EP0_IN_DATA_PHASE s...
      • 12. Repeat Steps 10 and 11 until all the data is transmitted or the last data packet is a short packet.
      • 13. If the last packet software sends is a short packet, it sets its internal state machine to EP0_END_XFER. If the last data pa...
      • 14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the UDDCS0[OPR] bit, which causes an interrupt.
      • 15. Software enters the ISR routine and determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is clear, and its internal state machine is EP0_END_XFER. Software clears the UDCCS0[OPR] bit and transfers its internal state machine to EP0_IDLE.
      • 16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
    • 12.5.2 Case 2: EP0 Control Read with a Premature Status Stage
      • 1. When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track endpoints stages when software communicates with the host PC.
      • 2. The host PC sends a SETUP command.
      • 3. UDC generates an EP0 Interrupt.
      • 4. Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.
      • 5. Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.
      • 6. Software parses the command in the buffer and determines that it is a Control Read.
      • 7. Software starts to load the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE.
      • 8. After it reads and parses the data, software clears the UDCCS0[SA] and the UDCCS0[OPR] bits and sets the UDCCS0[IPR] bit, if ...
      • 9. Software clears the UDC interrupt bit and returns from the interrupt service routine.
      • 10. The host PC issues an IN packet, which the UDC sends back to the host. After the host PC sends an ACK to the UDC, the UDC clears the UDDCS0[IPR] bit and generates an interrupt.
      • 11. Software enters the ISR routine and examines its internal state machine. It determines that it is in the EP0_IN_DATA_PHASE s...
      • 12. Repeat Steps 10 and 11 until all the data is transmitted or the last data packet is a short packet.
      • 13. As Steps 10 and 11 are repeated, the host sends a premature STATUS OUT stage, which indicates that the host PC can not accept more data, instead of an IN packet.
      • 14. When the EP0 interrupt occurs, software determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is cleared, and its machine state is EP0_IN_DATA_PHASE. This indicates that a premature STATUS OUT occurred.
      • 15. Software clears the UDCCS0[OPR] bit and changes the pin’s state to EP0_IDLE. The software writes to the UDCCS0[FTF] bit to clean up any buffer pointers and empty the transmit FIFO.
      • 16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
    • 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage
      • 1. When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track stages when software communicates with the host PC.
      • 2. The host PC sends a SETUP command.
      • 3. UDC generates an EP0 Interrupt.
      • 4. Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.
      • 5. Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.
      • 6. Software parses the command in the buffer and determines that it is a Control Write (such as Set Descriptor).
      • 7. Software sets the internal to EP0_OUT_DATA_PHASE and clears the UDCCS0[OPR] and UDCCS0[SA] bits.
      • 8. To allow a premature STATUS IN stage, software sets the UDCCS0[IPR] bit and loads a zero- length packet in the transmit FIFO.
      • 9. Software clears the UDC interrupt bit and returns from the interrupt service routine.
      • 10. The host PC issues an OUT packet and the UDC issues an EP0 interrupt.
      • 11. Software enters the ISR routine and determines that it is in the EP0_OUT_DATA_PHASE state, the UDCCS0[OPR] bit is set, and the UDCCS0[SA] bit is clear. This indicates that there is more data to receive.
      • 12. Software reads the data into a buffer while UDCCS0[RNE] bit is set and clears the UDDCCS0[OPR] bit.
      • 13. Software sets the UDCCS0[IPR] bit to allow a premature STATUS IN stage.
      • 14. Software clears the UDC interrupt bit and returns from the interrupt service routine.
      • 15. Steps 11 through 14 are repeated until all of the data is received.
      • 16. As Steps 11 through 14 are repeated, the host sends a STATUS IN stage, which indicates that the host PC can not send more data, instead of an OUT packet. The STATUS IN stage may be premature or not.
      • 17. Because software loaded a zero-length packet (see Step 8), the UDC responds to the STATUS IN by sending a a zero-length packet back to the host PC. This causes an interrupt.
      • 18. Software enters the ISR routine and determines that it is in the EP0_OUT_DATA_PHASE state and the UDCCS0[OPR] and UDCCS0[IPR] bits are clear. This indicates that a STATUS IN stage occurred.
      • 19. Software determines how many bytes were received before the interrupt and compares the number of received bytes to the wLeng...
      • 20. Software changes its internal state machine to EP0_IDLE.
      • 21. Software clears the UDC interrupt bit and returns from the interrupt service routine.
    • 12.5.4 Case 4: EP0 No Data Command
      • 1. When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track stages when software communicates with the host PC.
      • 2. The host PC sends a SETUP command.
      • 3. UDC generates an EP0 Interrupt.
      • 4. Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.
      • 5. Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.
      • 6. Software parses the data in the buffer and determines that it is a No Data command.
      • 7. Software executes the command and sets its internal state machine to EP0_IDLE. Software clears the UDCCS0[IPR] and UDCCS0[SA]...
      • 8. When the host PC executes the STATUS IN stage, the UDC sends back a zero-length packet, which indicates a successful handshake. This does not cause an interrupt.
    • 12.5.5 Case 5: EP1 Data Transmit (BULK-IN)
      • 12.5.5.1 Software Enables the DMA
        • 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP1 interrupt. The DMA start address must be aligned on a 16-byte boundary.
        • a. If the packet size is 64 bytes, software transfers the all the data in one DMA descriptor and sets the UDCCS1[TSP] bit in the second DMA descriptor.
        • b. If the packet size is less than 64 bytes, software sets up a string of descriptors in which the odd numbered descriptors point to the data and the even numbered descriptors are writes to the UDCCS1[TSP] bit.
        • 2. The host PC sends a BULK-IN and the UDC sends a data packet back to the host PC.
        • 3. The UDC generates an interrupt that is masked from the core.
        • 4. The DMA engine fills the EP1 data FIFO (UDDR1) with data and sets the UDCCS1[TSP] bit if the data packet is a short packet.
        • 5. Steps 2 through 4 repeat until all the bulk data is sent to the host PC.
      • 12.5.5.2 Software Enables the EP1 Interrupt
        • 1. During the SETUP VENDOR command, software fills the EP1 data FIFO (UDDR1) with data and clears the UDCCS1[TPC] bit. If the data packet is a short packet, software also sets the UDCCS1[TSP] bit.
        • 2. The host PC sends a BULK-IN and the UDC sends a data packet back to the host PC and generates an EP1 Interrupt.
        • 3. Software fills the EP1 data FIFO (UDDR1) with data and clears the UDCCS1[TPC] bit. If the data packet is a short packet, software also sets the UDCCS1[TSP] bit.
        • 4. Return from interrupt.
        • 5. Steps 2 through 4 repeat until all of the data is sent to the host PC.
    • 12.5.6 Case 6: EP2 Data Receive (BULK-OUT)
      • 12.5.6.1 Software Enables the DMA:
        • 1. During the SETUP VENDOR command, software sets up the DMA engine and sets the UDCCS2[DME] bit.
        • a. If the packet size is 32 or 64 bytes, software sets up a string of descriptors, each with a length of modulo 32 or 64. Software sets the interrupt bit for the appropriate descriptor.
        • b. If the packet size is less than 32 bytes, software uses interrupt mode.
        • 2. The host PC sends a BULK-OUT.
        • 3. The DMA engine reads data from the EP2 data FIFO (UDDR2).
        • 4. Steps 2 and 3 repeat until all the data has been read from the host.
        • 5. If the software receives an EP2 interrupt it completes this process:
        • a. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length packet.
        • b. If UDCCS2[RNE] is set, the data packet was a short packet and software must use the UDCWC2 count register to read the proper amount of data from the EP2 data FIFO (UDDR2).
        • c. Software clears the UDCCS2[RPC] bit.
        • 6. Return from interrupt.
      • 12.5.6.2 Software Allows the Core to Handle the Transaction
        • 1. During the SETUP VENDOR command, software clears the UDCCS2[DME] bit.
        • 2. The host PC sends a BULK-OUT and the UDC generates an EP2 Interrupt.
        • 3. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length packet.
        • 4. If UDCCS2[RNE] is set, software uses the UDCWC2 count register to read the proper amount of data from the EP2 data FIFO (UDDR2).
        • 5. Software clears the UDCCS2[RPC] bit.
        • 6. Return from interrupt.
        • 7. Steps 2 through 6 repeat until all the data has been read from the host.
    • 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
      • 12.5.7.1 Software Enables DMA
        • 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary.
        • a. If the packet size is 256 bytes, software transfers the all the data in one DMA descriptor.
        • b. If the packet size is less than 256 bytes, software sets up a string of descriptors in which the odd numbered descriptors point to the data and the even numbered descriptors are writes to the UDCCS1[TSP] bit.
        • 2. The host PC sends an ISOC-IN and the UDC sends a data packet back to the host PC.
        • 3. The UDC generates an interrupt that is masked from the core.
        • 4. The DMA engine fills the EP3 data FIFO (UDDR3) with data and sets the UDCCS3[TSP] bit if the data packet is a short packet.
        • 5. Steps 2 through 4 repeat until all the data has been sent to the host.
      • 12.5.7.2 Software Enables the EP3 Interrupt
        • 1. During the SETUP VENDOR command, software fills the EP3 data FIFO (UDDR3) with data and clears the UDCCS3[TPC] bit. If the data packet is a short packet, software also sets the UDCCS3[TSP] bit.
        • 2. The host PC sends a ISOC-IN command and the UDC sends a data packet back to the host PC and generates an EP3 Interrupt.
        • 3. Software fills the EP3 data FIFO (UDDR3) with data and clears the UDCCS3[TPC] bit. If the data packet is a short packet, software also sets the UDCCS3[TSP] bit.
        • 4. Return from interrupt.
        • 5. Steps 2 through 4 repeat until all of the data is sent to the host PC.
      • 12.5.7.3 Software Enables the SOF Interrupt
        • 1. Software disables the UDCCS3 Interrupt by setting UICR0[IM3] to a 1 and enables the SOF interrupt in the UFNHR register by setting UFNHR[SIM] to a 0.
        • 2. When the host PC sends an SOF, the UDC sets the UFNHR[SIR] bit, which causes an SOF interrupt.
        • 3. Software checks the UDCCS3[TFS] bit to determine if there is room for a data packet. If there is room, software fills the EP3...
        • 4. Software clears the UFNHR[SIR] bit.
        • 5. Return from interrupt.
        • 6. Steps 2 through 5 repeat until all the data is sent to the host PC.
    • 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
      • 12.5.8.1 Software Enables the DMA
        • 1. During the SETUP VENDOR command, software enables the DMA engine and sets the UDCCS4[DME] bit. ISO packet sizes are not restricted, but a packet size of modulo 32 is highly recommended efficiency.
        • a. If the packet size is between 32 and 256 bytes and is divisible by 32, software determines the number of descriptors needed and sets up a string of descriptors. Software sets the interrupt bit for the appropriate descriptor.
        • b. If the packet size is between 32 and 256 bytes and is not divisible by 32, software sets up a descriptor to receive each data packet, then reads the remaining data on each UDCCS2[RSP] bit interrupt and sets up another descriptor.
        • c. If the packet size is less than 32 bytes, software must use interrupt mode.
        • 2. The host PC sends a ISOC-OUT.
        • 3. The DMA engine reads the data from the EP4 data FIFO (UDDR4).
        • 4. Steps 2 and 3 repeat until all the data has been read from the host.
        • 5. If the software receives an EP4 interrupt it completes the following process:
        • a. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet.
        • b. If UDCCS4[RNE] is set, the data packet was a short packet and software uses the UDCWC4 count register to read the proper amount of data from the EP4 data FIFO (UDDR4).
        • c. Software clears the UDCCS4[RPC] bit.
        • 6. Return from interrupt.
      • 12.5.8.2 Software Allows the Core to Handle the Transaction
        • 1. During the SETUP VENDOR command, software clears the UDCCS4[DME] bit.
        • 2. The host PC sends a ISOC-OUT and the UDC generates an EP4 Interrupt.
        • 3. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet.
        • 4. If UDCCS4[RNE] is set, software uses the UDCWC4 count register to read the proper amount of data from the EP4 data FIFO (UDDR4).
        • 5. Software clears the UDCCS4[RPC] bit.
        • 6. Return from interrupt.
        • 7. Steps 2 through 6 repeat until all the data has been read from the host.
      • 12.5.8.3 Software Enables the SOF Interrupt
        • 1. Software disables the UDCCS4 Interrupt by setting UICR0[IM4] to a 1 and enables the SOF interrupt in the UFNHR register by setting UFNHR[SIM] to a 0.
        • 2. When the host PC sends an SOF, the UDC sets the UFNHR[SIR] bit, which causes an SOF interrupt.
        • 3. If UDCCS4[RNE] is clear and UDCCS4[RSP] is clear, no data packet was received.
        • 4. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet.
        • 5. If UDCCS4[RNE] is set, the data packet was a short packet and software uses the UDCWC4 count register to read the proper amount of data from the EP4 data FIFO (UDDR4).
        • 6. Software clears the UDCCS4[RPC] and UFNHR[SIR] bits.
        • 7. Return from interrupt.
        • 8. Steps 2 through 7 repeat until all the data is sent to the host PC.
    • 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)
      • 1. During the SETUP VENDOR command, software fills the EP5 data FIFO (UDDR5) with data and clears the UDCCS5[TPC] bit.
      • 2. The host PC sends an INTERRUPT-IN and the UDC generates an EP5 Interrupt.
      • 3. Software fills the EP5 data FIFO (UDDR5) with data and clears the UDCCS5[TPC] bit. If the data packet is a short packet, software also sets the UDCCS5[TSP] bit.
      • 4. Return from interrupt.
      • 5. Steps 2 through 4 repeat until all the data is sent to the host PC.
    • 12.5.10 Case 10: RESET Interrupt
      • 1. After a system reset, software loads the registers with the required values.
      • 2. Software enables the UDC by setting the UDCCR[UDE] bit and immediately reads the UDCCR[UDA] bit to determine if a USB reset is currently on the USB bus.
      • a. If UDCCR[UDA] is a 0, there is currently a USB reset on the bus and software clears the interrupt by writing a 1 to the UDCCR[RSTIR] bit. Software enables future reset interrupts by clearing the UDCCR[REM] bit.
      • b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables future reset interrupts by clearing the UDCCR[REM] bit.
      • 3. Return from interrupt.
      • 4. The host either asserts a USB reset or negates a USB reset.
      • 5. The UDC generates a reset interrupt.
      • 6. Software determines that the UDCCR[RSTIR] bit is set and clears the interrupt by writing a 1 to the UDCCR[RSTIR] bit. Software then examines the UDCCR[UDA] bit to determine the type of reset that took place:
      • a. If UDCCR[UDA] is a 0, a reset assertion took place. Software returns from the interrupt and waits for the reset negation interrupt.
      • b. If UDDCR[UDA] is a 1, a reset negation took place. Software sets any initialization that is necessary.
      • 7. Return from interrupt.
    • 12.5.11 Case 11: SUSPEND Interrupt
      • 1. As software starts, it clears the UDCCR[SRM] bit to allow a USB suspend interrupt.
      • 2. The host PC asserts a USB suspend by stopping activity on the UDC+ and UDC- signals.
      • 3. The UDC generates a suspend interrupt.
      • 4. Software determines that the UDCCR[SUSIR] bit is set.This indicates that a USB suspend has occurred and software takes any ne...
    • 12.5.12 Case 12: RESUME Interrupt
      • 1. As software starts, it clears the UDCCR[SRM] bit to allow a USB resume.
      • 2. The host PC asserts a USB resume by resuming activity after a suspend state on the UDC+ and UDC- signals.
      • 3. The UDC generates a resume interrupt.
      • 4. Software determines that the UDCCR[RESIR] bit is set. This indicates that a USB resume has occurred and the OS may take any n...
  • 12.6 UDC Register Descriptions
    • 12.6.1 UDC Control Register
      • 12.6.1.1 UDC Enable
      • 12.6.1.2 UDC Active
      • 12.6.1.3 UDC Resume (RSM)
      • 12.6.1.4 Resume Interrupt Request (RESIR)
      • 12.6.1.5 Suspend Interrupt Request (SUSIR)
      • 12.6.1.6 Suspend/Resume Interrupt Mask (SRM)
      • 12.6.1.7 Reset Interrupt Request (RSTIR)
      • 12.6.1.8 Reset Interrupt Mask (REM)
        • Table 12-12. UDC Control Register (Sheet 1 of 2)
    • 12.6.2 UDC Endpoint 0 Control/Status Register (UDCCS0)
      • 12.6.2.1 OUT Packet Ready (OPR)
      • 12.6.2.2 IN Packet Ready (IPR)
      • 12.6.2.3 Flush Tx FIFO (FTF)
      • 12.6.2.4 Device Remote Wake Up Feature (DRWF)
      • 12.6.2.5 Sent Stall (SST)
      • 12.6.2.6 Force Stall (FST)
      • 12.6.2.7 Receive FIFO Not Empty (RNE)
      • 12.6.2.8 Setup Active (SA)
        • Table 12-13. UDC Endpoint 0 Control Status Register
    • 12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11
      • 12.6.3.1 Transmit FIFO Service (TFS)
      • 12.6.3.2 Transmit Packet Complete (TPC)
      • 12.6.3.3 Flush Tx FIFO (FTF)
      • 12.6.3.4 Transmit Underrun (TUR)
      • 12.6.3.5 Sent STALL (SST)
      • 12.6.3.6 Force STALL (FST)
      • 12.6.3.7 Bit 6 Reserved
      • 12.6.3.8 Transmit Short Packet (TSP)
        • Table 12-14. UDC Endpoint x Control Status Register, Where x is 1, 6 or 11
    • 12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12
      • 12.6.4.1 Receive FIFO Service (RFS)
      • 12.6.4.2 Receive Packet Complete (RPC)
      • 12.6.4.3 Bit 2 Reserved
      • 12.6.4.4 DMA Enable (DME)
      • 12.6.4.5 Sent Stall (SST)
      • 12.6.4.6 Force Stall (FST)
      • 12.6.4.7 Receive FIFO Not Empty (RNE)
      • 12.6.4.8 Receive Short Packet (RSP)
        • Table 12-15. UDC Endpoint x Control Status Register, Where x is 2, 7, or 12 (Sheet 1 of 2)
    • 12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13
      • 12.6.5.1 Transmit FIFO Service (TFS)
      • 12.6.5.2 Transmit Packet Complete (TPC)
      • 12.6.5.3 Flush Tx FIFO (FTF)
      • 12.6.5.4 Transmit Underrun (TUR)
      • 12.6.5.5 Bit 4 Reserved
      • 12.6.5.6 Bit 5 Reserved
      • 12.6.5.7 Bit 6 Reserved
      • 12.6.5.8 Transmit Short Packet (TSP)
        • Table 12-16. UDC Endpoint x Control Status Register, Where x is 3, 8, or 13
    • 12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14
      • 12.6.6.1 Receive FIFO Service (RFS)
      • 12.6.6.2 Receive Packet Complete (RPC)
      • 12.6.6.3 Receive Overflow (ROF)
      • 12.6.6.4 DMA Enable (DME)
      • 12.6.6.5 Bit 4 Reserved
      • 12.6.6.6 Bit 5 Reserved
      • 12.6.6.7 Receive FIFO Not Empty (RNE)
      • 12.6.6.8 Receive Short Packet (RSP)
        • Table 12-17. UDC Endpoint x Control Status Register, Where x is 4, 9, or 14
    • 12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15.
      • 12.6.7.1 Transmit FIFO Service (TFS)
      • 12.6.7.2 Transmit Packet Complete (TPC)
      • 12.6.7.3 Flush Tx FIFO (FTF)
      • 12.6.7.4 Transmit Underrun (TUR)
      • 12.6.7.5 Sent STALL (SST)
      • 12.6.7.6 Force STALL (FST)
      • 12.6.7.7 Bit 6 Reserved
      • 12.6.7.8 Transmit Short Packet (TSP)
        • Table 12-18. UDC Endpoint x Control Status Register, Where x is 5, 10, or 15
    • 12.6.8 UDC Interrupt Control Register 0 (UICR0)
      • 12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
        • Table 12-19. UDC Interrupt Control Register 0
    • 12.6.9 UDC Interrupt Control Register 1 (UICR1)
      • 12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
        • Table 12-20. UDC Interrupt Control Register 1
    • 12.6.10 UDC Status/Interrupt Register 0 (USIR0)
      • 12.6.10.1 Endpoint 0 Interrupt Request (IR0)
      • 12.6.10.2 Endpoint 1 Interrupt Request (IR1)
      • 12.6.10.3 Endpoint 2 Interrupt Request (IR2)
      • 12.6.10.4 Endpoint 3 Interrupt Request (IR3)
      • 12.6.10.5 Endpoint 4 Interrupt Request (IR4)
      • 12.6.10.6 Endpoint 5 Interrupt Request (IR5)
      • 12.6.10.7 Endpoint 6 Interrupt Request (IR6)
      • 12.6.10.8 Endpoint 7 Interrupt Request (IR7)
        • Table 12-21. UDC Status / Interrupt Register 0
    • 12.6.11 UDC Status/Interrupt Register 1 (USIR1)
      • 12.6.11.1 Endpoint 8 Interrupt Request (IR8)
      • 12.6.11.2 Endpoint 9 Interrupt Request (IR9)
      • 12.6.11.3 Endpoint 10 Interrupt Request (IR10)
      • 12.6.11.4 Endpoint 11 Interrupt Request (IR11)
      • 12.6.11.5 Endpoint 12 Interrupt Request (IR12)
      • 12.6.11.6 Endpoint 13 Interrupt Request (IR13)
      • 12.6.11.7 Endpoint 14 Interrupt Request (IR14)
      • 12.6.11.8 Endpoint 15 Interrupt Request (IR15)
        • Table 12-22. UDC Status / Interrupt Register 1
    • 12.6.12 UDC Frame Number High Register (UFNHR)
      • 12.6.12.1 UDC Frame Number MSB (FNMSB)
      • 12.6.12.2 Isochronous Packet Error Endpoint 4 (IPE4)
      • 12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9)
      • 12.6.12.4 Isochronous Packet Error Endpoint 14 (IPE14)
      • 12.6.12.5 Start of Frame Interrupt Mask (SIM)
      • 12.6.12.6 Start of Frame Interrupt Request (SIR)
        • Table 12-23. UDC Frame Number High Register (Sheet 1 of 2)
    • 12.6.13 UDC Frame Number Low Register (UFNLR)
      • Table 12-24. UDC Frame Number Low Register
    • 12.6.14 UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14.
      • 12.6.14.1 Endpoint x Byte Count (BC[7:0])
        • Table 12-25. UDC Byte Count Register x, Where x is 2, 4, 7, 9, 12, or 14
    • 12.6.15 UDC Endpoint 0 Data Register (UDDR0)
      • Table 12-26. UDC Endpoint 0 Data Register
    • 12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11
      • Table 12-27. UDC Endpoint x Data Register, Where x is 1, 6, or 11
    • 12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12
      • Table 12-28. UDC Endpoint x Data Register, Where x is 2, 7, or 12
    • 12.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13
      • Table 12-29. UDC Endpoint x Data Register, where x is 3, 8, or 13
    • 12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14
      • Table 12-30. UDC Endpoint x Data Register, Where x is 4, 9, or 14
    • 12.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 15
      • Table 12-31. UDC Endpoint x Data Register, Where x is 5, 10, or 15
    • 12.6.21 UDC Register Locations
      • Table 12-32. UDC Control, Data, and Status Register Locations (Sheet 1 of 2)
• AC97 Controller Unit 13
  • 13.1 Overview
    • Note: The ACUNIT, I2S Controller, and the ASSP may not be used at the same time.
  • 13.2 Feature List
  • 13.3 Signal Description
    • Table 13-1. External Interface to Codecs
    • 13.3.1 Signal Configuration Steps
      • 1. Configure SYNC and SDATA_OUT as outputs.
      • 2. Configure BITCLK, SDATA_IN_0, and SDATA_IN_1 as inputs.
      • 3. nACRESET is a GPIO that is out of reset a dedicated output. It remains asserted on power-up. Complete these steps to de-assert nACRESET:
      • a. Configure the other AC97 signals as previously described.
      • b. In the Global Control Register (GCR), Set the GCR[COLD_RST] bit. Refer to Table 13-8, “Global Control Register” on page 13-20 for more details.
      • Note: Refer to Section 4.1.3, “GPIO Register Definitions” on page 4-7 for details on programing the GPDR and GAFR for use with the ACUNIT.
    • 13.3.2 Example AC-link
      • Figure 13-1. Data Transfer Through the AC-link
  • 13.4 AC-link Digital Serial Interface Protocol
    • Table 13-2. Supported Data Stream Formats (Sheet 1 of 2)
      • Figure 13-2. AC97 Standard Bidirectional Audio Frame
    • 13.4.1 AC-link Audio Output Frame (SDATA_OUT)
      • Figure 13-3. AC-link Audio Output Frame
      • Figure 13-4. Start of Audio Output Frame
      • Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and right sample stream time slots are filled with identical data.
      • 13.4.1.1 Slot 0: Tag Phase
      • 13.4.1.2 Slot 1: Command Address Port
        • 1. Set the Valid Frame bit (slot 0, bit 15)
        • 2. Set the valid bits for slots 1 and 2 (slot 0, bits 14 and 13)
        • 3. Write 0b00 to the codec ID field (slot 0, bits 1 and 0)
        • 4. Specify the read/write direction of the access (slot 1, bit 19).
        • 5. Specify the index to the codec register (slot 1, bits 18-12)
        • 6. If the access is a write, write the data to the command data port (slot 2, bits 19-4)
        • 1. Set the Valid Frame bit (slot 0, bit 15)
        • 2. Clear the valid bits for slots 1 and 2 (slot 0, bits 14 and 13)
        • 3. Write a non-zero value (0b01, 0b10, 0b11) to the codec ID field (slot 0, bits 1 and 0)
        • 4. Specify the read/write direction of the access (slot 1, bit 19).
        • 5. Specify the index to the codec register (slot 1, bits 18-12)
        • 6. If the access is a write, write the data to the command data port (slot 2, bits 19-4).
        • Table 13-3. Slot 1 Bit Definitions
      • 13.4.1.3 Slot 2: Command Data Port
        • Table 13-4. Slot 2 Bit Definitions
      • 13.4.1.4 Slot 3: PCM Playback Left Channel
      • 13.4.1.5 Slot 4: PCM Playback Right Channel
      • 13.4.1.6 Slot 5: Modem Line Codec
      • 13.4.1.7 Slots 6-11: Reserved
      • 13.4.1.8 Slot 12: I/O Control
        • 1. Slot 12 is initially marked invalid by default.
        • 2. A write to address 0x54 in codec I/O space transfers the data out of slot 12 in the next frame and slot 12 is marked valid. The data is also sent out on slots 1 and 2.
        • 3. After the first write to address 0x54, slot 12 remains valid for all subsequent frames. The data transmitted on slot 12 is the data last written to address 0x54. Any subsequent write to the register sends the new data out on the next frame.
        • 4. Following a system reset or AC97 cold reset, slot 12 is invalidated. Slot 12 remains invalid until the next write to the address 0x54.
    • 13.4.2 AC-link Audio Input Frame (SDATA_IN)
      • Figure 13-5. AC97 Input Frame
      • Figure 13-6. Start of an Audio Input Frame
      • 13.4.2.1 Slot 0: Tag Phase
      • 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits
        • Table 13-5. Input Slot 1 Bit Definitions
          • Note: Slot requests for slots 3 and 4 are always set or cleared in tandem (both set or both cleared).
      • 13.4.2.3 Slot 2: Status Data Port
        • Table 13-6. Input Slot 2 Bit Definitions
          • Note: If slot 2 is tagged invalid, the ACUNIT fills the entire slot with zeroes.
      • 13.4.2.4 Slot 3: PCM Record Left Channel
      • 13.4.2.5 Slot 4: PCM Record Right Channel
      • 13.4.2.6 Slot 5: Optional Modem Line Codec
      • 13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
      • 13.4.2.8 Slots 7-11: Reserved
      • 13.4.2.9 Slot 12: I/O Status
  • 13.5 AC-link Low Power Mode
    • 13.5.1 Powering Down the AC-link
      • Figure 13-7. AC-link Powerdown Timing
    • 13.5.2 Waking up the AC-link
      • 13.5.2.1 Wake up triggered by the Codec
        • Figure 13-8. SDATA_IN Wake Up Signaling
          • 1. After SDATA_IN goes high, SYNC must be held for a minimum of 1 mSec.
          • 2. The minimum SDATA_IN wake up pulse width is 1 mSec.
          • 3. BITCLK not to scale
      • 13.5.2.2 Wake Up Triggered by the ACUNIT
  • 13.6 ACUNIT Operation
    • Note: After it is enabled, the ACUNIT requests the DMA immediately to fill the transmit FIFO.
    • Note: The ACUNIT registers do not store the status of the DMA requests or information regarding the number of data samples in each FIFO. As a result, programmed I/O must not be used in place of DMA requests for data transfers.
    • 13.6.1 Initialization
      • 1. Program the GPIO Direction register and GPIO Alternate Function Select register to assign proper pin directions for the ACUNIT ports. Refer to Section 13.3, “Signal Description” for details.
      • 2. Set the GCR[COLD_RST] bit to deassert nACRESET. Until this is done, all other registers remain in a reset state. Deasserting nACRESET has the following effects:
      • a. Frames filled with zeroes are transmitted because the transmit FIFO is still empty. This situation does not cause an error condition.
      • b. The ACUNIT records zeroes until the codec sends in valid data.
      • c. DMA requests are enabled.
      • 3. Enable the primary ready interrupt enable or the secondary ready interrupt enable by setting the GCR[PRIRDY_IEN] or the GCR[SECRDY_IEN] bits, respectively.
      • 4. Software enables DMA operation in response to primary and secondary ready interrupts.
      • 5. The ACUNIT triggers transmit DMA requests. The DMA fills the transmit FIFO in response.
      • 6. The ACUNIT continues to transmit zeroes until the transmit FIFO is half full. When it is half full, valid FIFO data is sent across the AC-link.
      • Note: When nACRESET is deasserted, a read to the codec mixer register returns the type of hardware that resides in the codec. If...
    • 13.6.2 Trailing bytes
    • 13.6.3 Operational Flow for Accessing Codec Registers
      • 1. Software issues a dummy read to the codec register. The ACUNIT responds to this read operation with invalid data. The ACUNIT then initiates the read access across the AC-link.
      • 2. When the codec read operation completes, the ACUNIT sets GSR[SDONE] to a 1. For details, refer to Table 13-9, “Global Status Register”. Software clears this bit by writing a 1 it.
      • 3. Software repeats the read operation as detailed in Step 1. The ACUNIT now returns the data sent by the codec. The second read operation also initiates a read access across the AC-link.
      • 4. The ACUNIT times-out the read operation if the codec fails to respond in four SYNC frames. In this case, the second read operation returns a timed-out data value of 0x0000_FFFF.
  • 13.7 Clocks and Sampling Frequencies
  • 13.8 Functional Description
    • 13.8.1 FIFOs
      • 13.8.1.1 Transmit FIFO Errors
      • 13.8.1.2 Receive FIFO Errors
    • 13.8.2 Interrupts
    • 13.8.3 Registers
      • Note: Register tables show organization and individual bit definitions. All reserved bits are read as unknown values and must be written with a 0. A question mark indicates the value is unknown at reset.
      • Note: Some register bits receive status from codecs. The codec status sets the bit and software clears the bit (write a 1 to cle...
      • 13.8.3.1 Register Mapping Summary
        • Table 13-7. Register Mapping Summary (Sheet 1 of 2)
      • 13.8.3.2 Global Control Register
        • Table 13-8. Global Control Register (Sheet 1 of 2)
      • 13.8.3.3 Global Status Register (GSR)
        • Table 13-9. Global Status Register (Sheet 1 of 2)
      • 13.8.3.4 PCM-Out Control Register (POCR)
        • Table 13-10. PCM-Out Control Register
      • 13.8.3.5 PCM-In Control Register (PICR)
        • Table 13-11. PCM-In Control Register (PICR)
      • 13.8.3.6 PCM-Out Status Register (POSR)
        • Table 13-12. PCM-Out Status Register
          • 1. No more valid buffer data available for transmits.
          • 2. Buffer data available but DMA controller has excessive bandwidth requirements.
      • 13.8.3.7 PCM_In Status Register (PISR)
        • Table 13-13. PCM_In Status Register
      • 13.8.3.8 Codec Access Register (CAR)
        • Table 13-14. Codec Access Register
      • 13.8.3.9 PCM Data Register (PCDR)
        • Table 13-15. PCM Data Register
          • Figure 13-9. PCM Transmit and Receive Operation
      • 13.8.3.10 Mic-In Control Register (MCCR)
        • Table 13-16. Mic-In Control Register
      • 13.8.3.11 Mic-In Status Register (MCSR)
        • Table 13-17. Mic-In Status Register
      • 13.8.3.12 Mic-In Data Register (MCDR)
        • Table 13-18. Mic-In Data Register
          • Figure 13-10. Mic-in Receive-Only Operation
      • 13.8.3.13 Modem-Out Control Register (MOCR)
        • Table 13-19. Modem-Out Control Register
      • 13.8.3.14 Modem-In Control Register (MICR)
        • Table 13-20. Modem-In Control Register
      • 13.8.3.15 Modem-Out Status Register (MOSR)
        • Table 13-21. Modem-Out Status Register
          • 1. No more valid buffer data available for transmits.
          • 2. Buffer data available but DMA controller has excessive bandwidth requirements.
      • 13.8.3.16 Modem-In Status Register (MISR)
        • Table 13-22. Modem-In Status Register
      • 13.8.3.17 Modem Data Register (MODR)
        • Table 13-23. Modem Data Register
          • Figure 13-11. Modem Transmit and Receive Operation
      • 13.8.3.18 Accessing Codec Registers
        • Table 13-24. Address Mapping for Codec Registers (Sheet 1 of 2)
• Inter-Integrated Circuit Sound Controller 14
  • 14.1 Overview
  • 14.2 Signal Descriptions
    • Table 14-1. External Interface to CODEC
      • 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 for details regarding the GPDR.
      • 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR)” on page 4-17 for details regarding the GAFR.
      • 3. Program the BCKD bit in the I2SC’s Serial Audio Control Register. See Section 14.6.1, “Serial Audio Controller Global Control Register (SACR0)” for more details.
      • Note: Modifying the status of the SACR0[BCKD] bit during normal operation can cause jitter on the BITCLK and can affect serial activity.
        • 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 for details regarding the GPDR.
        • 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR)” on page 4-17 for details regarding the GAFR.
        • 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 for details regarding the GPDR.
        • 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR)” on page 4-17 for details regarding the GAFR.
        • 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 for details regarding the GPDR.
        • 2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6, “GPIO Alternate Function Register (GAFR)” on page 4-17 for details regarding the GAFR.
  • 14.3 Controller Operation
    • 14.3.1 Initialization
      • 1. Set the BITCLK direction by programming the SYSUNIT’s GPIO Direction register, the SYSUNIT’s GPIO Alternate Function Select register, and the I2SC’s Serial Audio Controller Global Control register (bit 2).
      • 2. Choose between Normal I2S or MSB-Justified modes of operation. This can be done by programming bit 0 of Serial Audio Controll...
      • 3. Optional: Programmed I/O may be used for priming the transmit FIFO with a few samples (ranging from 1 to 16). If the I2SLINK ...
      • 4. The following control bits can be simultaneously programmed in the I2SC’s Serial Audio Controller Global Control register (SACR0):
      • a. Enable I2SLINK by setting the ENB bit (bit-0) of SACR0.
      • b. Since the SACR0 register will be over-written in Step2, maintain BITCLK direction as programmed in Step1. Modifying BITCLK direction will glitch the clock and affect I2SLINK activity.
      • c. Program transmit and receive threshold levels by programming the TFTH and RFTH bits of SACR0[11:8] and SACR0(15:12), respectively. See Section 14.6.1.2, “Suggested TFTH and RFTH for DMA servicing”, regarding permitted threshold levels.
    • 14.3.2 Disabling and Enabling Audio Replay
      • 1. All I2SLINK replay activity is disabled. The frame or data sample, in the midst of which the replay is disabled, will have in...
      • 2. Transmit FIFO pointers are reset to zero.
      • 3. Transmit FIFO fill-level is reset to zero.
      • 4. Zeros are transmitted across the I2SLINK.
      • 5. Transmit DMA requests are disabled.
    • 14.3.3 Disabling and Enabling Audio Record
      • 1. I2SLINK recording activity is disabled. The frame or data sample, in the midst of which the recording is disabled, could have...
      • 2. Receive FIFO pointers are reset to zero.
      • 3. Receive FIFO fill-level is reset to zero.
      • 4. Any read operations by the DMA/CPU are returned with zeros.
      • 5. Receive DMA requests are disabled.
    • 14.3.4 Transmit FIFO Errors
      • 1. Valid transmit data is still available in memory, but the DMA controller starves the transmit FIFO, as it is busy servicing other higher-priority peripherals.
      • 2. The DMA controller has transferred all valid data from memory to the transmit FIFO.
    • 14.3.5 Receive FIFO Errors
    • 14.3.6 Trailing Bytes
  • 14.4 Serial Audio Clocks and Sampling Frequencies
    • Table 14-2. Supported Sampling Frequencies
  • 14.5 Data Formats
    • 14.5.1 FIFO and Memory Format
    • 14.5.2 I2S and MSB-Justified Serial Audio Formats
      • Figure 14-1. I2S Data Formats (16 bits)
      • Figure 14-2. MSB-Justified Data Formats (16 bits)
  • 14.6 I2S Controller Register Descriptions
    • 14.6.1 Serial Audio Controller Global Control Register (SACR0)
      • Table 14-3. SACR0 Bit Descriptions (Sheet 1 of 2)
      • 14.6.1.1 Special purpose FIFO Read/Write function
        • Table 14-4. FIFO Write/Read table
      • 14.6.1.2 Suggested TFTH and RFTH for DMA servicing
        • Table 14-5. TFTH and RFTH Values for DMA Servicing
    • 14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)
      • Table 14-6. SACR1 Bit Descriptions
    • 14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
      • Table 14-7. SASR0 Bit Descriptions
    • 14.6.4 Serial Audio Clock Divider Register (SADIV)
      • Note: Setting this register to values other than those shown in Table 14-2, “Supported Sampling Frequencies” on page 14-6 is not allowed and will cause unpredictable activity.
      • Table 14-8. SADIV Bit Descriptions
    • 14.6.5 Serial Audio Interrupt Clear Register (SAICR)
      • Table 14-9. SAICR Bit Descriptions
    • 14.6.6 Serial Audio Interrupt Mask Register (SAIMR)
      • Table 14-10. SAIMR Bit Descriptions
    • 14.6.7 Serial Audio Data Register (SADR)
      • Table 14-11. SADR Bit Descriptions
        • Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR
    • 14.6.8 Controller: Register Memory Map
      • Table 14-12. Register Memory Map
  • 14.7 Interrupts
    • Note: For further details, see Section 14.6.3, “Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)”.
• MultiMediaCard Controller 15
  • 15.1 Overview
    • Figure 15-1. MMC System Interaction
    • Table 15-1. Command Token Format
    • Table 15-2. MMC Data Token Format
    • Table 15-3. SPI Data Token Format
      • Figure 15-2. MMC Mode Operation Without Data Token
      • Figure 15-3. MMC Mode Operation With Data Token
      • Figure 15-4. SPI Mode Operation Without Data Token
      • Figure 15-5. SPI Mode Read Operation
      • Figure 15-6. SPI Mode Write Operation
      • Note: One- and three-byte data transfers are not supported with this controller. Data transfers of 10 or more bytes are supported for stream writes only.
  • 15.2 MultiMediaCard Controller Functional Description
    • 15.2.1 Signal Description
      • Table 15-4. MMC Signal Description
    • 15.2.2 MultiMediaCard Controller Reset
    • 15.2.3 Card Initialization Sequence
    • 15.2.4 MMC and SPI Modes
      • 15.2.4.1 MMC Mode
      • 15.2.4.2 SPI Mode
        • Note: When the card is in SPI mode, the only way to return to MMC mode is by toggling the power to the card.
    • 15.2.5 Error Detection
    • 15.2.6 Interrupts
    • 15.2.7 Clock Control
      • 1. Stop the clock.
      • 2. Write the registers.
      • 3. Restart the clock.
      • Warning: Stopping the clock while data is in the transmit or receive FIFOs will cause unpredictable results.
    • 15.2.8 Data FIFOs
      • 15.2.8.1 Response Data FIFO (MMC_RES)
      • 15.2.8.2 Receive Data FIFO, MMC_RXFIFO
      • 15.2.8.3 Transmit Data FIFO, MMC_TXFIFO
      • 15.2.8.4 DMA and Program I/O
  • 15.3 Card Communication Protocol
    • 15.3.1 Basic, No Data, Command and Response Sequence
      • 1. Stop the clock
      • 2. Write 0x6f to the MMC_I_MASK register and wait for and verify the MMC_I_REG[CLK_IS_OFF] interrupt
      • 3. Write to the following registers, as necessary:
      • 4. Start the clock
      • 5. Write 0x7b to the MMC_I_MASK register and wait for and verify the MMC_I_REG[END_CMD_RES] interrupt
      • 6. Read the MMC_RES FIFO and MMC_STAT registers
    • 15.3.2 Data Transfer
      • 15.3.2.1 Block Data Write
      • 15.3.2.2 Block Data Read
      • 15.3.2.3 Stream Data Write
      • 15.3.2.4 Stream Data READ
    • 15.3.3 Busy Sequence
    • 15.3.4 SPI Functionality
      • Note: The clock must be stopped before writing to any registers as described in Section 15.3.1, “Basic, No Data, Command and Response Sequence”.
  • 15.4 MultiMediaCard Controller Operation
    • 15.4.1 Start and Stop Clock
      • 1. Write 0x01 in MMC_STRPCL to stop the MMC clock.
      • 2. Write 0x0f in MMC_I_MASK to mask all interrupts except the MMC_I_REG[CLK_IS_OFF] interrupt.
      • 3. Wait for the MMC_I_REG[CLK_IS_OFF] interrupt.
    • 15.4.2 Initialize
    • 15.4.3 Enabling SPI Mode
      • 1. MMC_SPI[SPI_EN] must be set to 1.
      • 2. MMC_SPI[SPI_CS_EN] must be set to 1.
      • 3. MMC_SPI[SPI_CS_ADDRESS] must be set to specify the card that the software wants to address. A 1 enables CS0 and a 0 enables CS1.
      • Note: When the card is in SPI mode, the only way to return to MMC mode is by toggling power to the card.
    • 15.4.4 No Data Command and Response Sequence
      • 1. Turn the clock off, as described in chapter in Section 15.4.1, “Start and Stop Clock”.
      • 2. Write the command index in the MMC_CMD[CMD_INDEX] bits.
      • 3. Write the command argument in the MMC_ARGH and MMC_ARGL registers.
      • 4. Write the MMC_CMDAT register set as follows:
      • a. Write 0b00 to MMC_CMDAT[RESPONSE_FORMAT].
      • b. Clear the MMC_CMDAT[DATA_EN] bit.
      • c. Clear the MMC_CMDAT[BUSY] bit, unless the card may respond busy.
      • d. Clear the MMC_CMDAT[INIT] bit.
      • 5. Write MMC_RESTO register with the appropriate value.
      • 6. Write 0x1b in MMC_I_MASK to unmask the MMC_I_REG[END_CMD_RES] interrupt.
      • 7. Start the clock, as described in Section 15.4.1, “Start and Stop Clock”
    • 15.4.5 Erase
    • 15.4.6 Single Data Block Write
      • 1. Wait for the response as described in section Section 15.4.4, “No Data Command and Response Sequence”.
      • 2. Write data to the MMC_TXFIFO FIFO and continue until all of the data has been written to the FIFO.
      • Note: If a piece of data smaller than 32 bytes is written to the FIFO, the MMC_PRTBUF register must be set.
        • 3. Set MMC_I_MASK register to 0x1e and wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
        • 4. Set MMC_I_MASK to 0x1d.
        • 5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another command sequence on a different card.
        • 6. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
    • 15.4.7 Single Block Read
      • 1. Wait for the response as described in section Section 15.4.4, “No Data Command and Response Sequence”.
      • 2. Read data from the MMC_RXFIFO FIFO, as data becomes available in the FIFO, and continue reading until all data is read from the FIFO.
      • 3. Set MMC_I_MASK to 0x1e.
      • 4. Wait for the MMC_I_REG[DATA_TRAN_DONE] interrupt.
      • 5. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
    • 15.4.8 Multiple Block Write
    • 15.4.9 Multiple Block Read
    • 15.4.10 Stream Write
      • 1. Wait for the response as described in section Section 15.4.4, “No Data Command and Response Sequence”.
      • 2. Write data to the MMC_TXFIFO FIFO and continue until all of the data is written to the FIFO.
      • Note: When data less than 32 bytes is written to the FIFO, the MMC_PRTBUF[BUF_PART_FULL] bit must be set.
        • 3. Set MMC_I_MASK to 0x77 and wait for MMC_I_REG[STOP_CMD] interrupt.
        • 4. Set the command registers for a stop transaction command (CMD12).
        • 5. Wait for a response to the stop transaction command as described in section Section 15.4.4, “No Data Command and Response Sequence”.
        • 6. Set MMC_I_MASK to 0x1e.
        • 7. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
        • 8. Set MMC_I_MASK to 0x1d.
        • 9. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] interrupt or start another command sequence on a different card.
        • 10. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
    • 15.4.11 Stream Read
      • 1. Wait for the response as described in section Section 15.4.4, “No Data Command and Response Sequence”.
      • 2. Read data from the MMC_RXFIFO FIFO and continue until all of the data has been read from the FIFO.
      • 3. Set the command registers for a stop transaction command (CMD12). If the DMA is being used, the last descriptor must set the DMA to send an interrupt to signal that all the data has been read.
      • 4. Wait for a response to the stop transaction command as described in section Section 15.4.4, “No Data Command and Response Sequence”
      • 5. Set MMC_I_MASK to 0x1e.
      • 6. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
      • 7. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
  • 15.5 MultiMediaCard Controller Register Descriptions
    • Table 15-5. MMC Controller Registers
    • 15.5.1 MMC_STRPCL Register
      • Table 15-6. MMC_STRPCL Register
    • 15.5.2 MMC_STAT Register
      • Table 15-7. MMC_STAT Register (Sheet 1 of 2)
    • 15.5.3 MMC_CLKRT Register
      • Table 15-8. MMC_CLK Register
    • 15.5.4 MMC_SPI Register
      • Table 15-9. MMC_SPI Register (Sheet 1 of 2)
    • 15.5.5 MMC_CMDAT Register
      • Table 15-10. MMC_CMDAT Register (Sheet 1 of 2)
    • 15.5.6 MMC_RESTO Register
      • Table 15-11. MMC_RESTO Register
    • 15.5.7 MMC_RDTO Register
      • Table 15-12. MMC_RDTO Register
    • 15.5.8 MMC_BLKLEN Register
      • Table 15-13. MMC_BLKLEN Register
    • 15.5.9 MMC_NOB Register
      • Table 15-14. MMC_NOB Register
    • 15.5.10 MMC_PRTBUF Register
      • Table 15-15. MMC_PRTBUF Register
    • 15.5.11 MMC_I_MASK Register
      • Table 15-16. MMC_I_MASK Register
    • 15.5.12 MMC_I_REG Register
      • Table 15-17. MMC_I_REG Register
    • 15.5.13 MMC_CMD Register
      • Table 15-18. MMC_CMD Register
      • Table 15-19. Command Index Values (Sheet 1 of 3)
    • 15.5.14 MMC_ARGH Register
      • Table 15-20. MMC_ARGH Register
    • 15.5.15 MMC_ARGL Register
      • Table 15-21. MMC_ARGL Register
    • 15.5.16 MMC_RES FIFO (read only)
      • Table 15-22. MMC_RES, FIFO Entry
    • 15.5.17 MMC_RXFIFO FIFO (read only)
      • Table 15-23. MMC_RXFIFO, FIFO Entry
    • 15.5.18 MMC_TXFIFO FIFO
      • Table 15-24. MMC_TXFIFO, FIFO Entry
• Network/Audio Synchronous Serial Protocol Serial Ports 16
  • 16.1 Overview
  • 16.2 Features
  • 16.3 Signal Description
    • Table 16-1. SSP Serial Port I/O Signals
  • 16.4 Operation
    • 16.4.1 Processor and DMA FIFO Access
    • 16.4.2 Trailing Bytes in the Receive FIFO
      • 16.4.2.1 Time-out
      • 16.4.2.2 Removing Trailing Bytes
        • Note: The time-out interrupt must be enabled by setting SSCR1[TINTE].
    • 16.4.3 Data Formats
      • Note: The serial clock (SSPSCLK), if driven by the SSP port, toggles only while an active data transfer is underway, unless rece...
      • 16.4.3.1 TI Synchronous Serial Protocol* Details
        • Figure 16-1. Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers)
        • Figure 16-2. Texas Instruments Synchronous Serial Frame* Protocol (single transfers)
      • 16.4.3.2 SPI Protocol Details
        • Figure 16-3. Motorola SPI* Frame Protocol (multiple transfers)
          • Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of ...
          • Note: The phase and polarity of SSPSCLK can be configured for four different modes. This example shows just one of those modes (SSCR1[SPO] = 0, SSCR1[SPH] = 0).
        • Figure 16-4. Motorola SPI* Frame Protocol (single transfers)
          • Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of ...
          • Note: SSCR1[SPH] is ignored for all data frame formats except for the Motorola SPI* protocol.
        • Figure 16-5. Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers)
          • Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of ...
        • Figure 16-6. Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)
          • Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of ...
      • 16.4.3.3 Microwire* Protocol Details
        • Figure 16-7. National Semiconductor Microwire* Frame Protocol (multiple transfers)
          • Note: When configured master the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB) or it drives zero, ...
        • Figure 16-8. National Semiconductor Microwire* Frame Protocol (single transfers)
          • Note: When configured master the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB) or it drives zero, ...
      • 16.4.3.4 PSP Details
        • Figure 16-9. Programmable Serial Protocol (multiple transfers)
        • Figure 16-10. Programmable Serial Protocol (single transfers)
        • Table 16-2. Programmable Serial Protocol (PSP) Parameters
          • Note: The SSPSFRM delay must not extend beyond the end of T4. SSPSFRM Width must be asserted for at least 1 SSPSCLK, and must be...
    • 16.4.4 Hi-Z on SSPTXD
      • 16.4.4.1 TI Synchronous Serial Port
        • Figure 16-11. TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0
        • Figure 16-12. TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1
          • Note: If SSPSCLK is an input, the device driving SSPSCLK must provide another clock edge to cause the TXD line to go to Hi-Z.
      • 16.4.4.2 Motorola SPI
        • Figure 16-13. Motorola SPI with SSCR[TTE]=1
          • Note: SSCR1[TTELP] must be 0 for Motorola SPI.
      • 16.4.4.3 National Semiconductor Microwire
        • Figure 16-14. National Semiconductor Microwire with SSCR1[TTE]=1
          • Note: SSCR1[TTELP] must be 0 for National Semiconductor Microwire.
      • 16.4.4.4 Programmable Serial Protocol
        • Figure 16-15. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame)
        • Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)
        • Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)
    • 16.4.5 FIFO Operation
      • 16.4.5.1 Using Programmed I/O Data Transfers
      • 16.4.5.2 Using DMA Data Transfers
    • 16.4.6 Baud-Rate Generation
  • 16.5 SSP Port Register Descriptions
    • Note: Write the SSP port registers after a reset but before the SSP port is enabled.
    • 16.5.1 SSP Control Register 0 (SSCR0)
      • Table 16-3. SSCR0 Bit Definitions (Sheet 1 of 2)
    • 16.5.2 SSP Control Register 1 (SSCR1)
      • Table 16-4. SSCR1 Bit Definitions (Sheet 1 of 6)
    • 16.5.3 SSP Programmable Serial Protocol Register (SSPSP)
      • Table 16-5. SSPSP Bit Definitions (Sheet 1 of 2)
    • 16.5.4 SSP Time Out Register (SSTO)
      • Table 16-6. SSTO Bit Definitions
    • 16.5.5 SSP Interrupt Test Register (SSITR)
      • Table 16-7. SSITR Bit Definitions (Sheet 1 of 2)
    • 16.5.6 SSP Status Register (SSSR)
      • Table 16-8. SSSR Bit Definitions (Sheet 1 of 3)
    • 16.5.7 SSP Data Register (SSDR)
      • Table 16-9. SSDR Bit Definitions
  • 16.6 Register Summary
    • Table 16-10. NSSP Register Address Map
    • Table 16-11. ASSP Register Address Map
• Hardware UART 17
  • This chapter describes the signal definitions and operation of the Intel® PXA26x Processor Family Hardware UART (HWUART) port.
  • The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO) pins or the BTUART pins. When using the...
  • The HWUART is configured differently than the other UARTs. The HWUART adds support for full hardware flow control.
  • 17.1 Overview
    • The HWUART contains a UART and a slow infrared transmit encoder and receive decoder that conforms to the IrDA Serial Infrared (SIR) Physical Layer Link Specification.
    • The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-...
    • The HWUART operates in FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit FIFO holds data from the processor until it is tr...
    • The HWUART also supports using DMA to transfer data to and from the HWUART.
    • The UART includes a programmable baud rate generator that can divide the input clock by 1 to 216-1. This produces a 16X clock th...
  • 17.2 Features
    • The HWUART has the following features:
  • 17.3 Signal Descriptions
    • Table 17-1 lists and describes each external signal that is connected to the UART module. The pins are connected to the PXA26x processor family through GPIOs. Refer to Section 4.1, “General- Purpose Input/Output” for details on the GPIOs.
    • Table 17-1. UART Signal Descriptions
  • 17.4 Operation
    • The format of a UART data frame is shown in Figure 17-1.
    • Figure 17-1. Example UART Data Frame
      • Receive data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is created by the baud rate gene...
      • Each data frame is between seven and 12 bits long, depending on the size of the data programmed, whether parity is enabled, and ...
      • The UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and eight bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking errors.
      • The UART can use NRZ coding to represent individual bit values. NRZ coding is enabled when the Interrupt Enable Register’s (IER)...
    • Figure 17-2. Example NRZ Bit Encoding (0b0100 1011)
    • 17.4.1 Reset
      • The UART is disabled on reset. To enable the UART, software must program the GPIO registers (see Section 4.1, “General-Purpose I...
      • When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops transmitting or receiving more data. Data in the FIFO is not cleared and transmission resumes when the UART is enabled.
    • 17.4.2 FIFO Operation
      • The UART has a transmit FIFO and a receive FIFO each holding 64 characters of data. There are three separate methods for moving data into/out of the FIFOs: interrupts, polling, and DMA.
      • 17.4.2.1 FIFO Interrupt Mode Operation
        • For a receive interrupt to occur, the receive FIFO and receive interrupts must be enabled. The Interrupt Identification Register...
        • The receiver line status interrupt (IIR = 0xC6) has the highest priority and the received data available interrupt (IIR = 0xC4) is lower. The line status interrupt occurs only when the character at the front of the FIFO has errors.
        • The data ready bit (DR in the Line Status Register) is set when a character is transferred from the shift register to the receive FIFO. The DR bit is cleared when the FIFO is empty.
        • A character timeout interrupt occurs when the receive FIFO and receive timeout interrupt are enabled and all of the following conditions exist:
        • After the processor reads one character from the receive FIFO or a new start bit is received, the timeout interrupt is cleared a...
        • Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is cleared when the THR is written or the IIR is read.
      • 17.4.2.2 FIFO Polled Mode Operation
        • When the FIFOs are enabled, clearing both IER[DMAE] and IER[4:0] places the serial port in FIFO polled operating mode. The recei...
        • The processor can also check the LSR[TEMT] (transmitter empty) bit, which is set when the transmit FIFO and Holding register are empty.
      • 17.4.2.3 FIFO DMA Mode Operation
        • The UART has two DMA requests: One for transmit data service, and one for receive data service. DMA requests are generated in FIFO mode only. The requests are activated by setting IER[DMAE].
      • 17.4.2.4 DMA Receive Programming Errors
        • If the DMA channel stops prematurely due to the end of a descriptor chain or other error, the processor must be notified, since ...
      • 17.4.2.5 DMA Error Handling
        • An error interrupt is used when DMA requests are enabled. The interrupt is generated when LSR bit 7 is set to 1. This happens wh...
        • Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if an error interrupt exist...
          • If an error occurs while in DMA mode:
          • The processor must now read out the error bytes through programmed I/O (PIO). When all errors have been removed from the FIFO, the receive DMA requests are once again enabled automatically by the UART.
          • If an error occurs when the receive FIFO trigger threshold has been reached such that a receive DMA request is set, users need to wait for the DMA to finish the transfer before reading out the error bytes through PIO. If not, FIFO underflow could occur.
        • Note: Ensure that the DMA controller has completed the previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO. If not, FIFO underflow could occur.
      • 17.4.2.6 Removing Trailing Bytes In DMA Mode
        • When the number of entries in the receive FIFO is less than its trigger threshold, and no additional data is received, the remai...
    • 17.4.3 Autoflow Control
      • Autoflow Control uses the Clear-to-Send (nCTS) and Request-to-Send (nRTS) signals to automatically control the flow of data betw...
      • Autoflow mode can be used in two ways: full autoflow, automating both nCTS and nRTS; and half autoflow, automating only nCTS. Fu...
      • When in full autoflow mode, nRTS is asserted when the UART FIFO is ready to receive data from the remote transmitter. This occur...
      • When in Full or Half-Autoflow mode, nCTS is asserted by the remote receiver when the receiver is ready to receive data from the ...
      • Note: Autoflow mode can be used only in conjunction with FIFO mode.
    • 17.4.4 Auto-Baud-Rate Detection
      • The HWUART supports auto-baud-rate detection. When enabled, the UART counts the number of 14.7456-MHz-clock cycles within the st...
      • If the UART is to program the Divisor Latch registers, users can choose between two methods for auto-baud calculation: table-bas...
      • When the baud rate is detected, the auto-baud circuitry will disable itself by clearing the ABR[ABE]. If users want to re-enable auto-baud detection, ABR[ABE] must be set.
      • Note: Auto-baud rate detection is not supported with IrDA (Slow Infrared) Mode.
        • See Section 17.5.8, “Auto-Baud Control Register (ABR)” for more information on auto-baud.
    • 17.4.5 Slow Infrared Asynchronous Interface
      • The Slow Infrared (SIR) interface is used to support two-way wireless communication that uses infrared transmission. The SIR pro...
      • The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins attached to the SIR only hav...
      • 17.4.5.1 Operation
        • The SIR modulation technique works with 5-, 6-, 7-, or 8-bit characters with an optional parity bit. The data is preceded by a z...
        • Figure 17-3. IR Transmit and Receive Example
          • The top line in Figure 17-3 shows an asynchronous transmission as it is sent from the UART. The second line shows the pulses gen...
          • When XMODE is cleared, each zero bit has a pulse width of 3/16 of a bit time. When XMODE is set, a pulse of 1.6 ms is generated ...
        • Figure 17-4. XMODE Example.
        • Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check t...
          • To disable SIR, disable the IrDA LED first, if possible. Second, set the TXD GPIO pin to the infrared LED's default state using ...
  • 17.5 Hardware UART Register Descriptions
    • 17.5.1 Receive Buffer Register (RBR)
      • In non-FIFO mode, the Receive Buffer Register (RBR) holds the character(s) received by the UART’s Receive Shift Register. If the...
      • In FIFO mode, the RBR latches the value of the data byte at the front of the FIFO (see Table 17-2).
      • Table 17-2. RBR Bit Definitions
    • 17.5.2 Transmit Holding Register (THR)
      • In non-FIFO mode, the Transmit Holding Register (THR) holds the data byte(s) to be transmitted next. When the Transmit Shift Reg...
      • In FIFO mode, a write to the THR puts data into the end of the FIFO. The data at the front of the FIFO is loaded to the TSR when that register is empty. The Transmit Holding Register bit definitions are shown in Table 17-3.
      • Table 17-3. THR Bit Definitions
    • 17.5.3 Divisor Latch Registers (DLL and DLH)
      • The HWUART contains a programmable baud rate generator that can take the 14.7456 MHz-fixed- input clock and divide it by a numbe...
      • The baud rate of the data shifted in to or out of a UART is given by the formula:
      • For example, if the divisor is 24, the baud rate is 38400 bps.
      • The divisor’s reset value is 0x0002.
      • Table 17-4 and Table 17-5 describe the DLL and DLH registers.
      • Table 17-4. Divisor Latch Register Low (DLL) Bit Definitions
      • Table 17-5. Divisor Latch Register High (DLH) Bit Definitions
    • 17.5.4 Interrupt Enable Register (IER)
      • The IER enables the five types of interrupts that set a value in the Interrupt Identification Register (IIR). To disable an interrupt, software must clear the appropriate bit in the IER. Software can enable some interrupts by setting the appropriate bit.
      • The Character Timeout Indication interrupt is separated from the received data available interrupt to ensure that the processor ...
      • Enabling DMA requests also enables a separate error interrupt. For additional information see Section 17.4.2.5.
      • Bit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ coding enable control bits. Bits ...
      • Note: MCR[OUT2] is a global interrupt enable, and must be set to enable UART interrupts.
      • Table 17-6. IER Bit Definitions (Sheet 1 of 2)
        • Note: To ensure that the DMA controller and programmed I/O do not access the same FIFO, software must not set the DMAE while the TIE or RAVIE bits are set to a 1.
    • 17.5.5 Interrupt Identification Register (IIR)
      • The UART prioritizes interrupts in four levels (see Table 17-7, “Interrupt Conditions”) and records them in the IIR. The IIR sto...
      • If additional data is received before a receiver time out interrupt is serviced, the interrupt is deasserted.
      • Read IIR to determine the type and source of UART interrupts. To be 16550 compatible, the lower 4 bits of the IIR are priority e...
      • IIR[nIP] indicates the existence of an interrupt in the lower four bits of the IIR. A low signal on this bit indicates an encode...
      • Table 17-7. Interrupt Conditions
      • Table 17-8. IIR Bit Definitions (Sheet 1 of 2)
        • Table 17-9 shows the priority, type, and source of the Interrupt Identification Register Interrupts. It also gives the reset condition used to deassert the Interrupts. Bits (0-3) of the IIR represent priority encoded interrupts. Bits (4-7) do not.
      • Table 17-9. Interrupt Identification Register Decode (Sheet 1 of 2)
    • 17.5.6 FIFO Control Register (FCR)
      • The FIFO Control Register (FCR) is a write-only register that is located at the same address as the IIR, which is a read-only re...
      • Table 17-10. FCR Bit Definitions (Sheet 1 of 2)
    • 17.5.7 Receive FIFO Occupancy Register (FOR)
      • The Receive FIFO Occupancy Register shows the number of bytes currently remaining in the receive FIFO. It can be used by the pro...
      • All reserved bits are read as unknown and must be written with a 0. The register organization and the individual bit definitions are shown in Table 17-11 on page 17-19.
      • Table 17-11. FOR Bit Definitions
    • 17.5.8 Auto-Baud Control Register (ABR)
      • The ABR controls the functionality and options for auto-baud-rate detection within the UART. Through this register, users can en...
      • The auto-baud circuitry counts the number of clocks in the start bit and writes this count into the Auto-Baud Count Register (AC...
      • Note: Auto-baud rate detection is not supported with slow infrared Mode.
      • Table 17-12. ABR Bit Definitions
        • See Section 17.4.4, “Auto-Baud-Rate Detection” for more information on auto-baud rate.
    • 17.5.9 Auto-Baud Count Register (ACR)
      • The ACR stores the number of 14.7456-MHz-clock cycles within a start bit pulse. This value is then used by the processor or the ...
      • Table 17-13. ACR Bit Definitions
    • 17.5.10 Line Control Register (LCR)
      • The Line Control Register (LCR) specifies the format for the asynchronous data communications exchange. The serial data format c...
      • Table 17-14. LCR Bit Definitions (Sheet 1 of 2)
    • 17.5.11 Line Status Register (LSR)
      • The LSR provides data transfer status information to the processor.
      • In non-FIFO mode, LSR[4:2]: parity error, framing error, and break interrupt, show the error status of the character that has just been received.
      • In FIFO mode, LSR[4:2] show the status bits of the character that is currently at the front of the FIFO.
      • LSR[4:1] produce a receiver line status interrupt when the corresponding conditions are detected and the interrupt is enabled. I...
      • The LSR must be read before the erroneous character is read. LSR[4:1] bits are set until software reads the LSR.
      • See Section 17.4.2.3, “FIFO DMA Mode Operation” for details on using the DMA to receive data.
      • Table 17-15. LSR Bit Definitions (Sheet 1 of 3)
    • 17.5.12 Modem Control Register (MCR)
      • The Modem Control Register (MCR) uses the modem control pin nRTS to control the interface with a modem or data set. The MCR also...
      • Table 17-16. MCR Bit Definitions (Sheet 1 of 2)
    • 17.5.13 Modem Status Register (MSR)
      • The Modem Status Register (MSR) provides the current state of the control lines from the modem or data set (or a peripheral devi...
      • The status of the modem control lines do not affect the FIFOs. To use these lines for flow control, IER[MIE] must be set. When a...
      • Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IER[MIE] is set.
      • Table 17-17. MSR Bit Definitions
    • 17.5.14 Scratchpad Register (SPR)
      • The read/write Scratchpad Register has no effect on the UART. It is intended as a scratchpad register for use by the programmer. It is included for 16550A compatibility. The SPR bit definitions are shown in Table 17-18.
      • Table 17-18. SPR Bit Definitions
    • 17.5.15 Infrared Selection Register (ISR)
      • Each UART can manage an IrDA module associated with it. The Infrared Selection Register controls IrDA functions (see Section 17.4.5, “Slow Infrared Asynchronous Interface” on page 17-8). The ISR bit definitions are shown in Table 17-19.
      • Table 17-19. ISR Bit Definitions (Sheet 1 of 2)
  • 17.6 Hardware UART Register Summary
    • Table 17-20 contains the register addresses for the HWUART.
    • Table 17-20. HWUART Register Locations (Sheet 1 of 2)
• Internal Flash 18
  • Note: This section describes the synchronous Intel StrataFlash® memory. All references to Intel StrataFlash® memory is to the synchronous (K3) version.
  • 18.1 Initialization
    • 18.1.1 Intel StrataFlash® Memory Reset Configuration
      • Figure 18-1. Flash Memory Reset Using State Machine
      • Figure 18-2. Flash Memory Reset Logic if Watchdog Reset is Not Necessary
    • 18.1.2 BOOT_SEL[2:0] Configuration
    • 18.1.3 Determining the Size and Configuration of Flash Using Software
    • 18.1.4 SXCNFG Configuration
      • Table 18-1. SXCNFG Configuration for Internal Flash
        • Warning: Using a memory-clock frequency above 133 MHz is not allowed in synchronous mode with Intel StrataFlash® memory.
    • 18.1.5 Configuring the Intel StrataFlash® Memory
      • Table 18-2. RCR Values for Each PXA26x processor family Applications Processor Version
        • Warning: The CAS latency setting within SXCNFG[SXCLx] is one less than the actual setting. For example, setting SXCNFG[SXCLx]=0b100 gives a CAS latency of 5 clocks. The CAS latency value programmed into the flash is also one less than the actual setting.
        • Note: The instructions to do the RCR configuration sequence and the SXCNFG above must either be in RAM or guaranteed not to fetc...
  • 18.2 Additional Intel StrataFlash® Memory Information