Document Outline

• TABLE OF CONTENTS
  • LIST OF FIGURES
  • LIST OF TABLES
• 1 DESCRIPTION
• 2 FEATURE HIGHLIGHTS
  • 2.1 General
  • 2.2 Microprocessor Interface
  • 2.3 HDLC Ethernet Mapping
  • 2.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping
  • 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver
  • 2.6 Committed Information Rate (CIR) Controller
  • 2.7 SDRAM Interface
  • 2.8 MAC Interface
  • 2.9 T1/E1/J1 Line Interface
  • 2.10 Clock Synthesizer
  • 2.11 Jitter Attenuator
  • 2.12 T1/E1/J1 Framer
  • 2.13 TDM Bus
  • 2.14 Test and Diagnostics
  • 2.15 Specifications Compliance
• 3 APPLICATIONS
• 4 ACRONYMS AND GLOSSARY
• 5 MAJOR OPERATING MODES
• 6 BLOCK DIAGRAMS
• 7 PIN DESCRIPTIONS
  • 7.1 Pin Functional Description
• 8 FUNCTIONAL DESCRIPTION
  • 8.1 Processor Interface
    • 8.1.1 Read-Write/Data Strobe Modes
    • 8.1.2 Clear on Read
    • 8.1.3 Interrupt and Pin Modes
• 9 ETHERNET MAPPER
  • 9.1 Ethernet Mapper Clocks
    • 9.1.1 Ethernet Interface Clock Modes
    • 9.1.2 Serial Interface Clock Modes
  • 9.2 Resets and Low Power Modes
  • 9.3 Initialization and Configuration
  • 9.4 Global Resources
  • 9.5 Per-Port Resources
  • 9.6 Device Interrupts
  • 9.7 Interrupt Information Registers
  • 9.8 Status Registers
  • 9.9 Information Registers
  • 9.10 Serial Interface
  • 9.11 Connections and Queues
  • 9.12 Arbiter
  • 9.13 Flow Control
    • 9.13.1 Full Duplex Flow Control
    • 9.13.2 Half Duplex Flow Control
    • 9.13.3 Host-Managed Flow Control
  • 9.14 Ethernet Interface Port
    • 9.14.1 DTE and DCE Mode
  • 9.15 Ethernet MAC
    • 9.15.1 MII Mode Options
    • p.15.2 RMII Mode
    • 9.15.3 PHY MII Management Block and MDIO Interface
  • 9.16 BERT in the Ethernet Mapper
    • 9.16.1 Receive Data Interface
      • 9.16.1.1 Receive Pattern Detection
      • 9.16.1.2 PRBS Synchronization
    • 9.16.2 Repetitive Pattern Synchronization
    • 9.16.3 Pattern Monitoring
    • 9.16.4 Pattern Generation
      • 9.16.4.1 Error Insertion
      • 9.16.4.2 Performance Monitoring Update
  • 9.17 Transmit Packet Processor
  • 9.18 Receive Packet Processor
  • 9.19 X.86 Encoding and Decoding
  • 9.20 Committed Information Rate Controller
• 10 INTEGRATED T1/E1/J1 TRANSCEIVER
  • 10.1 T1/E1/J1 Clocks
  • 10.2 Per-Channel Operation
  • 10.3 T1/E1/J1 Transceiver Interrupts
  • 10.4 T1 Framer/Formatter Control and Status
    • 10.4.1 T1 Transmit Transparency
    • 10.4.2 AIS-CI and RAI-CI Generation and Detection
    • 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation
  • 10.5 E1 Framer/Formatter Control and Status
    • 10.5.1 Automatic Alarm Generation
  • 10.6 Per-Channel Loopback
  • 10.7 Error Counters
    • 10.7.1 Line-Code Violation Counter (TR.LCVCR)
    • 10.7.2 Path Code Violation Count Register (TR.PCVCR)
    • 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR)
    • 10.7.4 E-Bit Counter (TR.EBCR)
  • 10.8 DS0 Monitoring Function
  • 10.9 Signaling Operation
    • 10.9.1 Processor-Based Receive Signaling
      • 10.9.1.1 Change-of-State
    • 10.9.2 Hardware-Based Receive Signaling
      • 10.9.2.1 Receive Signaling Reinsertion at RSERO
      • 10.9.2.2 Force Receive Signaling All Ones
      • 10.9.2.3 Receive Signaling Freeze
    • 10.9.3 Processor-Based Transmit Signaling
      • 10.9.3.1 T1 Mode
      • 10.9.3.2 E1 Mode
    • 10.9.4 Hardware-Based Transmit Signaling
  • 10.10 Per-Channel Idle Code Generation
    • 10.10.1 Idle-Code Programming Examples
  • 10.11 Channel Blocking Registers
  • 10.12 Elastic Stores Operation
    • 10.12.1 Receive Elastic Store
      • 10.12.1.1 T1 Mode
      • 10.12.1.2 E1 Mode
    • 10.12.2 Transmit Elastic Store
      • 10.12.2.1 T1 Mode
      • 10.12.2.2 E1 Mode
    • 10.12.3 Elastic Stores Initialization
    • 10.12.4 Minimum Delay Mode
  • 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
  • 10.14 T1 Bit-Oriented Code (BOC) Controller
    • 10.14.1 Transmit BOC
      • 10.14.1.1 Transmit a BOC
    • 10.14.2 Receive BOC
      • Receive a BOC
  • 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only)
    • 10.15.1 Method 1: Internal Register Scheme Based on Double-Frame
    • 10.15.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe
  • 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver
    • 10.16.1 HDLC Configuration
    • 10.16.2 FIFO Control
    • 10.16.3 HDLC Mapping
    • 10.16.4 FIFO Information
    • 10.16.5 Receive Packet-Bytes Available
      • 10.16.5.1 Receive HDLC Code Example
  • 10.17 Legacy FDL Support (T1 Mode)
    • 10.17.1 Overview
    • 10.17.2 Receive Section
    • 10.17.3 Transmit Section
  • 10.18 D4/SLC-96 Operation
  • 10.19 Programmable In-Band Loop Code Generation and Detection
  • 10.20 Line Interface Unit (LIU)
    • 10.20.1 LIU Operation
    • 10.20.2 Receiver
      • 10.20.2.1 Receive Level Indicator and Threshold Interrupt
      • 10.20.2.2 Receive G.703 Synchronization Signal (E1 Mode)
      • 10.20.2.3 Monitor Mode
    • 10.20.3 Transmitter
      • 10.20.3.1 Transmit Short-Circuit Detector/Limiter
      • 10.20.3.2 Transmit Open-Circuit Detector
      • 10.20.3.3 Transmit BPV Error Insertion
      • 10.20.3.4 Transmit G.703 Synchronization Signal (E1 Mode)
  • 10.21 MCLK Prescaler
  • 10.22 Jitter Attenuator
  • 10.23 CMI (Code Mark Inversion) Option
  • 10.24 Recommended Circuits
  • 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION
    • 10.25.1 BERT Status
    • 10.25.2 BERT Mapping
    • 10.25.3 BERT Repetitive Pattern Set
    • 10.25.4 BERT Bit Counter
    • 10.25.5 BERT Error Counter
    • 10.25.6 BERT Alternating Word-Count Rate
    • 10.26 Payload Error-Insertion Function (T1 Mode Only)
      • 10.26.1 Number-of-Errors Registers
  • 10.27 Programmable Backplane Clock Synthesizer
  • 10.28 Fractional T1/E1 Support
  • 10.29 T1/E1/J1 Transmit Flow Diagrams
• 11 DEVICE REGISTERS
  • 11.1 Register Bit Maps
    • 11.1.1 Global Ethernet Mapper Register Bit Map
    • 11.1.2 Arbiter Register Bit Map
    • 11.1.3 BERT Register Bit Map
    • 11.1.4 Serial Interface Register Bit Map
    • 11.1.5 Ethernet Interface Register Bit Map
    • 11.1.6 MAC Register Bit Map
  • 11.2 Global Register Definitions for Ethernet Mapper
  • 11.3 Arbiter Registers
    • 11.3.1 Arbiter Register Bit Descriptions
  • 11.4 BERT Registers
  • 11.5 Serial Interface Registers
    • 11.5.1 Serial Interface Transmit and Common Registers
      • 11.5.1.1 Serial Interface Transmit Register Bit Descriptions
      • 11.5.1.2 Transmit HDLC Processor Register Bit Descriptions
    • 11.5.2 X.86 Registers
    • 11.5.3 Receive Serial Interface
      • 11.5.3.1 Receive Serial Register Bit Descriptions
  • 11.6 Ethernet Interface Registers
    • Ethernet Interface Register Bit Descriptions
    • 11.6.2 MAC Registers
  • 11.7 T1/E1/J1 Transceiver Registers
    • 11.7.1 Number-of-Errors Left Register
• 12 FUNCTIONAL TIMING
  • 12.1 Functional Serial I/O Timing
  • 12.2 MII and RMII Interfaces
  • 12.3 Transceiver T1 Mode Functional Timing
  • 12.4 E1 Mode
• 13 OPERATING PARAMETERS
  • 13.1 Thermal Characteristics
  • 13.2 MII Interface
  • 13.3 RMII Interface
  • 13.4 MDIO Interface
  • 13.5 Transmit WAN Interface
  • 13.6 Receive WAN Interface
  • 13.7 SDRAM Timing
  • 13.8 Microprocessor Bus AC Characteristics
  • 13.9 AC Characteristics: Receive-Side
  • 13.10 AC Characteristics: Backplane Clock Timing
  • 13.11 AC Characteristics: Transmit Side
  • 13.12 JTAG Interface Timing
• 14 JTAG INFORMATION
  • 14.1 JTAG TAP Controller State Machine Description
  • 14.2 Instruction Register
  • 14.3 JTAG ID Codes
  • 14.4 Test Registers
    • 14.4.1 Boundary Scan Register
    • 14.4.2 Bypass Register
    • 14.4.3 Identification Register
  • 14.5 JTAG Functional Timing
• 15 PACKAGE INFORMATION
  • 15.1 256-Ball BGA (27mm x 27mm) (56-G6004-001)
• 16 DOCUMENT REVISION HISTORY