Document Outline

• DESCRIPTION
• FEATURE HIGHLIGHTS
  • General
  • Link Aggregation (Inverse Multiplexing)
  • HDLC
  • Committed Information Rate (CIR) Controller
  • X.86 Support
  • SDRAM Interface
  • MAC Interface
  • Microprocessor Interface
  • Test and Diagnostics
  • Specifications compliance
• APPLICATIONS
• ACRONYMS AND GLOSSARY
• MAJOR OPERATING MODES
• BLOCK DIAGRAMS
• PIN DESCRIPTIONS
  • Pin Functional Description
• FUNCTIONAL DESCRIPTION
  • Processor Interface
    • Read-Write/Data Strobe Modes
    • Clear on Read
    • Interrupt and Pin Modes
  • Clock Structure
    • Serial Interface Clock Modes
    • Ethernet Interface Clock Modes
  • Resets and Low-Power Modes
  • Initialization and Configuration
  • Global Resources
  • Per-Port Resources
  • Device Interrupts
  • Serial Interface
  • Link Aggregation (IMUX)
    • Microprocessor Requirements
    • IMUX Command Protocol
    • Out of Frame (OOF) Monitoring
    • Data Transfer
  • Connections and Queues
  • Arbiter
  • Flow Control
    • Full-Duplex Flow Control
    • Half-Duplex Flow control
    • Host-Managed Flow control
  • Ethernet Interface Port
    • DTE and DCE Mode
  • Ethernet MAC
    • MII Mode
    • RMII Mode
    • PHY MII Management Block and MDIO Interface
  • BERT
    • BERT Features
    • Receive Data Interface
      • Receive Pattern Detection
      • PRBS Synchronization
    • Repetitive Pattern Synchronization
    • Pattern Monitoring
    • Pattern Generation
      • Error Insertion
      • Performance Monitoring Update
  • Transmit Packet Processor
  • Receive Packet Processor
  • X.86 Encoding and Decoding
  • Committed Information Rate Controller
• DEVICE REGISTERS
  • Register Bit Maps
    • Global Register Bit Map
    • Arbiter Register Bit Map
    • BERT Register Bit Map
    • Serial Interface Register Bit Map
    • Ethernet Interface Register Bit Map
    • MAC Register Bit Map
  • Global Register Definitions
  • Arbiter Registers
    • Arbiter Register Bit Descriptions
  • BERT Registers
  • Serial Interface Registers
    • Serial Interface Transmit and Common Registers
    • Serial Interface Transmit Register Bit Descriptions
    • Transmit HDLC Processor Registers
    • X.86 Registers
    • Receive Serial Interface
  • Ethernet Interface Registers
    • Ethernet Interface Register Bit Descriptions
    • MAC Registers
• FUNCTIONAL TIMING
  • MII and RMII Interfaces
• OPERATING PARAMETERS
  • Thermal Characteristics
  • MII Interface
  • RMII Interface
  • MDIO Interface
  • Transmit WAN Interface
  • Receive WAN Interface
  • SDRAM Timing
  • Microprocessor Bus AC Characteristics
  • JTAG Interface Timing
• JTAG INFORMATION
  • JTAG TAP Controller State Machine Description
  • Instruction Register
    • SAMPLE:PRELOAD
    • BYPASS
    • EXTEST
    • CLAMP
    • HIGHZ
    • IDCODE
  • JTAG ID Codes
  • Test Registers
    • Boundary Scan Register
    • Bypass Register
    • Identification Register
  • JTAG Functional Timing
• PACKAGE INFORMATION
  • 169-Ball CSBGA, 14mm x 14mm (56-G6035-001)
• DOCUMENT REVISION HISTORY