Document Outline

• MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual
  • About This Book
    • Audience
    • Suggested Reading
      • General Information
      • ColdFire Documentation
    • Conventions
  • Chapter 1 Overview
    • 1.1 Key Features
      • 1.1.1 Version 2 ColdFire Core
        • 1.1.1.1 Cache
        • 1.1.1.2 SRAM
        • 1.1.1.3 Flash
        • 1.1.1.4 Debug Module
      • 1.1.2 System Control Module
      • 1.1.3 External Interface Module (EIM)
      • 1.1.4 Chip Select
      • 1.1.5 Power Management
      • 1.1.6 General Input/Output Ports
      • 1.1.7 Interrupt Controllers (INTC0/INTC1)
      • 1.1.8 SDRAM Controller
      • 1.1.9 Test Access Port
      • 1.1.10 UART Modules
      • 1.1.11 DMA Timers (DTIM0-DTIM3)
      • 1.1.12 General-Purpose Timers (GPTA/GPTB)
      • 1.1.13 Periodic Interrupt Timers (PIT0-PIT3)
      • 1.1.14 Software Watchdog Timer
      • 1.1.15 Phase Locked Loop (PLL)
      • 1.1.16 DMA Controller
      • 1.1.17 Reset
    • 1.2 MCF5282-Specific Features
      • 1.2.1 Fast Ethernet Controller (FEC)
      • 1.2.2 FlexCAN
      • 1.2.3 I2C Bus
      • 1.2.4 Queued Serial Peripheral Interface (QSPI)
      • 1.2.5 Queued Analog-to-Digital Converter (QADC)
  • Chapter 2 ColdFire Core
    • 2.1 Introduction
      • 2.1.1 Overview
    • 2.2 Memory Map/Register Description
      • 2.2.1 Data Registers (D0-D7)
      • 2.2.2 Address Registers (A0-A6)
      • 2.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)
      • 2.2.4 Condition Code Register (CCR)
      • 2.2.5 Program Counter (PC)
      • 2.2.6 Cache Control Register (CACR)
      • 2.2.7 Access Control Registers (ACRn)
      • 2.2.8 Vector Base Register (VBR)
      • 2.2.9 Status Register (SR)
      • 2.2.10 Memory Base Address Registers (RAMBAR, FLASHBAR)
    • 2.3 Functional Description
      • 2.3.1 Version 2 ColdFire Microarchitecture
      • 2.3.2 Instruction Set Architecture (ISA_A+)
      • 2.3.3 Exception Processing Overview
        • 2.3.3.1 Exception Stack Frame Definition
      • 2.3.4 Processor Exceptions
        • 2.3.4.1 Access Error Exception
        • 2.3.4.2 Address Error Exception
        • 2.3.4.3 Illegal Instruction Exception
        • 2.3.4.4 Divide-By-Zero
        • 2.3.4.5 Privilege Violation
        • 2.3.4.6 Trace Exception
        • 2.3.4.7 Unimplemented Line-A Opcode
        • 2.3.4.8 Unimplemented Line-F Opcode
        • 2.3.4.9 Debug Interrupt
        • 2.3.4.10 RTE and Format Error Exception
        • 2.3.4.11 TRAP Instruction Exception
        • 2.3.4.12 Unsupported Instruction Exception
        • 2.3.4.13 Interrupt Exception
        • 2.3.4.14 Fault-on-Fault Halt
        • 2.3.4.15 Reset Exception
      • 2.3.5 Instruction Execution Timing
        • 2.3.5.1 Timing Assumptions
        • 2.3.5.2 MOVE Instruction Execution Times
        • 2.3.5.3 Standard One Operand Instruction Execution Times
        • 2.3.5.4 Standard Two Operand Instruction Execution Times
        • 2.3.5.5 Miscellaneous Instruction Execution Times
        • 2.3.5.6 EMAC Instruction Execution Times
        • 2.3.5.7 Branch Instruction Execution Times
  • Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)
    • 3.1 Introduction
      • 3.1.1 Overview
        • 3.1.1.1 Introduction to the MAC
    • 3.2 Memory Map/Register Definition
      • 3.2.1 MAC Status Register (MACSR)
      • 3.2.2 Mask Register (MASK)
      • 3.2.3 Accumulator Registers (ACC0-3)
      • 3.2.4 Accumulator Extension Registers (ACCext01, ACCext23)
    • 3.3 Functional Description
      • 3.3.1 Fractional Operation Mode
        • 3.3.1.1 Rounding
        • 3.3.1.2 Saving and Restoring the EMAC Programming Model
        • 3.3.1.3 MULS/MULU
        • 3.3.1.4 Scale Factor in MAC or MSAC Instructions
      • 3.3.2 EMAC Instruction Set Summary
      • 3.3.3 EMAC Instruction Execution Times
      • 3.3.4 Data Representation
      • 3.3.5 MAC Opcodes
  • Chapter 4 Cache
    • 4.1 Introduction
      • 4.1.1 Features
      • 4.1.2 Introduction
    • 4.2 Memory Map/Register Definition
      • 4.2.1 Cache Control Register (CACR)
      • 4.2.2 Access Control Registers (ACR0, ACR1)
    • 4.3 Functional Description
      • 4.3.1 Interaction with Other Modules
      • 4.3.2 Memory Reference Attributes
      • 4.3.3 Cache Coherency and Invalidation
      • 4.3.4 Reset
      • 4.3.5 Cache Miss Fetch Algorithm/Line Fills
  • Chapter 5 Static RAM (SRAM)
    • 5.1 SRAM Features
    • 5.2 SRAM Operation
    • 5.3 SRAM Programming Model
      • 5.3.1 SRAM Base Address Register (RAMBAR)
      • 5.3.2 SRAM Initialization
      • 5.3.3 SRAM Initialization Code
      • 5.3.4 Power Management
  • Chapter 6 ColdFire Flash Module (CFM)
    • 6.1 Features
    • 6.2 Block Diagram
    • 6.3 Memory Map
      • 6.3.1 CFM Configuration Field
      • 6.3.2 Flash Base Address Register (FLASHBAR)
      • 6.3.3 CFM Registers
      • 6.3.4 Register Descriptions
        • 6.3.4.1 CFM Configuration Register (CFMCR)
        • 6.3.4.2 CFM Clock Divider Register (CFMCLKD)
        • 6.3.4.3 CFM Security Register (CFMSEC)
        • 6.3.4.4 CFM Protection Register (CFMPROT)
        • 6.3.4.5 CFM Supervisor Access Register (CFMSACC)
        • 6.3.4.6 CFM Data Access Register (CFMDACC)
        • 6.3.4.7 CFM User Status Register (CFMUSTAT)
        • 6.3.4.8 CFM Command Register (CFMCMD)
    • 6.4 CFM Operation
      • 6.4.1 Read Operations
      • 6.4.2 Write Operations
      • 6.4.3 Program and Erase Operations
        • 6.4.3.1 Setting the CFMCLKD Register
        • 6.4.3.2 Program, Erase, and Verify Sequences
        • 6.4.3.3 Flash Valid Commands
        • 6.4.3.4 Flash User Mode Illegal Operations
      • 6.4.4 Stop Mode
      • 6.4.5 Master Mode
    • 6.5 Flash Security Operation
      • 6.5.1 Back Door Access
      • 6.5.2 Erase Verify Check
    • 6.6 Reset
    • 6.7 Interrupts
  • Chapter 7 Power Management
    • 7.1 Features
    • 7.2 Memory Map and Registers
      • 7.2.1 Programming Model
      • 7.2.2 Memory Map
      • 7.2.3 Register Descriptions
        • 7.2.3.1 Low-Power Interrupt Control Register (LPICR)
        • 7.2.3.2 Low-Power Control Register (LPCR)
    • 7.3 Functional Description
      • 7.3.1 Low-Power Modes
        • 7.3.1.1 Run Mode
        • 7.3.1.2 Wait Mode
        • 7.3.1.3 Doze Mode
        • 7.3.1.4 Stop Mode
        • 7.3.1.5 Peripheral Shut Down
      • 7.3.2 Peripheral Behavior in Low-Power Modes
        • 7.3.2.1 ColdFire Core
        • 7.3.2.2 Static Random-Access Memory (SRAM)
        • 7.3.2.3 Flash
        • 7.3.2.4 System Control Module (SCM)
        • 7.3.2.5 SDRAM Controller (SDRAMC)
        • 7.3.2.6 Chip Select Module
        • 7.3.2.7 DMA Controller (DMAC0-DMA3)
        • 7.3.2.8 UART Modules (UART0, UART1, and UART2)
        • 7.3.2.9 I2C Module
        • 7.3.2.10 Queued Serial Peripheral Interface (QSPI)
        • 7.3.2.11 DMA Timers (DMAT0-DMAT3)
        • 7.3.2.12 Interrupt Controllers (INTC0, INTC1)
        • 7.3.2.13 Fast Ethernet Controller (FEC)
        • 7.3.2.14 I/O Ports
        • 7.3.2.15 Reset Controller
        • 7.3.2.16 Chip Configuration Module
        • 7.3.2.17 Clock Module
        • 7.3.2.18 Edge Port
        • 7.3.2.19 Watchdog Timer
        • 7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
        • 7.3.2.21 Queued Analog-to-Digital Converter (QADC)
        • 7.3.2.22 General Purpose Timers (GPTA and GPTB)
        • 7.3.2.23 FlexCAN
        • 7.3.2.24 ColdFire Flash Module
        • 7.3.2.25 BDM
        • 7.3.2.26 JTAG
      • 7.3.3 Summary of Peripheral State During Low-Power Modes
  • Chapter 8 System Control Module (SCM)
    • 8.1 Overview
    • 8.2 Features
    • 8.3 Memory Map and Register Definition
    • 8.4 Register Descriptions
      • 8.4.1 Internal Peripheral System Base Address Register (IPSBAR)
      • 8.4.2 Memory Base Address Register (RAMBAR)
      • 8.4.3 Core Reset Status Register (CRSR)
      • 8.4.4 Core Watchdog Control Register (CWCR)
      • 8.4.5 Core Watchdog Service Register (CWSR)
    • 8.5 Internal Bus Arbitration
      • 8.5.1 Overview
      • 8.5.2 Arbitration Algorithms
        • 8.5.2.1 Round-Robin Mode
        • 8.5.2.2 Fixed Mode
      • 8.5.3 Bus Master Park Register (MPARK)
    • 8.6 System Access Control Unit (SACU)
      • 8.6.1 Overview
      • 8.6.2 Features
      • 8.6.3 Memory Map/Register Definition
        • 8.6.3.1 Master Privilege Register (MPR)
        • 8.6.3.2 Peripheral Access Control Registers (PACR0-PACR8)
        • 8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1)
  • Chapter 9 Clock Module
    • 9.1 Features
    • 9.2 Modes of Operation
      • 9.2.1 Normal PLL Mode
      • 9.2.2 1:1 PLL Mode
      • 9.2.3 External Clock Mode
    • 9.3 Low-power Mode Operation
    • 9.4 Block Diagram
    • 9.5 Signal Descriptions
      • 9.5.1 EXTAL
      • 9.5.2 XTAL
      • 9.5.3 CLKOUT
      • 9.5.4 CLKMOD[1:0]
      • 9.5.5 RSTOUT
    • 9.6 Memory Map and Registers
      • 9.6.1 Module Memory Map
      • 9.6.2 Register Descriptions
        • 9.6.2.1 Synthesizer Control Register (SYNCR)
        • 9.6.2.2 Synthesizer Status Register (SYNSR)
    • 9.7 Functional Description
      • 9.7.1 System Clock Modes
      • 9.7.2 Clock Operation During Reset
      • 9.7.3 System Clock Generation
      • 9.7.4 PLL Operation
        • 9.7.4.1 Phase and Frequency Detector (PFD)
        • 9.7.4.2 Charge Pump/Loop Filter
        • 9.7.4.3 Voltage Control Output (VCO)
        • 9.7.4.4 Multiplication Factor Divider (MFD)
        • 9.7.4.5 PLL Lock Detection
        • 9.7.4.6 PLL Loss of Lock Conditions
        • 9.7.4.7 PLL Loss of Lock Reset
        • 9.7.4.8 Loss of Clock Detection
        • 9.7.4.9 Loss of Clock Reset
        • 9.7.4.10 Alternate Clock Selection
        • 9.7.4.11 Loss of Clock in Stop Mode
  • Chapter 10 Interrupt Controller Modules
    • 10.1 68K/ColdFire Interrupt Architecture Overview
      • 10.1.1 Interrupt Controller Theory of Operation
        • 10.1.1.1 Interrupt Recognition
        • 10.1.1.2 Interrupt Prioritization
        • 10.1.1.3 Interrupt Vector Determination
    • 10.2 Memory Map
    • 10.3 Register Descriptions
      • 10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)
      • 10.3.2 Interrupt Mask Register (IMRHn, IMRLn)
      • 10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
      • 10.3.4 Interrupt Request Level Register (IRLRn)
      • 10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
      • 10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))
        • 10.3.6.1 Interrupt Sources
      • 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)
    • 10.4 Prioritization Between Interrupt Controllers
    • 10.5 Low-Power Wakeup Operation
  • Chapter 11 Edge Port Module (EPORT)
    • 11.1 Introduction
    • 11.2 Low-Power Mode Operation
    • 11.3 Interrupt/General-Purpose I/O Pin Descriptions
    • 11.4 Memory Map and Registers
      • 11.4.1 Memory Map
      • 11.4.2 Registers
        • 11.4.2.1 EPORT Pin Assignment Register (EPPAR)
        • 11.4.2.2 EPORT Data Direction Register (EPDDR)
        • 11.4.2.3 Edge Port Interrupt Enable Register (EPIER)
        • 11.4.2.4 Edge Port Data Register (EPDR)
        • 11.4.2.5 Edge Port Pin Data Register (EPPDR)
        • 11.4.2.6 Edge Port Flag Register (EPFR)
  • Chapter 12 Chip Select Module
    • 12.1 Overview
    • 12.2 Chip Select Module Signals
    • 12.3 Chip Select Operation
      • 12.3.1 General Chip Select Operation
        • 12.3.1.1 8-, 16-, and 32-Bit Port Sizing
        • 12.3.1.2 External Boot Chip Select Operation
    • 12.4 Chip Select Registers
      • 12.4.1 Chip Select Module Registers
        • 12.4.1.1 Chip Select Address Registers (CSAR0-CSAR6)
        • 12.4.1.2 Chip Select Mask Registers (CSMR0-CSMR6)
        • 12.4.1.3 Chip Select Control Registers (CSCR0-CSCR6)
  • Chapter 13 External Interface Module (EIM)
    • 13.1 Features
    • 13.2 Bus and Control Signals
    • 13.3 Bus Characteristics
    • 13.4 Data Transfer Operation
      • 13.4.1 Bus Cycle Execution
      • 13.4.2 Data Transfer Cycle States
      • 13.4.3 Read Cycle
      • 13.4.4 Write Cycle
      • 13.4.5 Fast Termination Cycles
      • 13.4.6 Back-to-Back Bus Cycles
      • 13.4.7 Burst Cycles
        • 13.4.7.1 Line Transfers
        • 13.4.7.2 Line Read Bus Cycles
        • 13.4.7.3 Line Write Bus Cycles
    • 13.5 Misaligned Operands
  • Chapter 14 Signal Descriptions
    • 14.1 Overview
      • 14.1.1 Single-Chip Mode
      • 14.1.2 External Boot Mode
    • 14.2 External Signals
      • 14.2.1 External Interface Module (EIM) Signals
        • 14.2.1.1 Address Bus (A[23:0])
        • 14.2.1.2 Data Bus (D[31:0])
        • 14.2.1.3 Byte Strobes (BS[3:0])
        • 14.2.1.4 Output Enable (OE)
        • 14.2.1.5 Transfer Acknowledge (TA)
        • 14.2.1.6 Transfer Error Acknowledge (TEA)
        • 14.2.1.7 Read/Write (R/W)
        • 14.2.1.8 Transfer Size(SIZ[1:0])
        • 14.2.1.9 Transfer Start (TS)
        • 14.2.1.10 Transfer In Progress (TIP)
        • 14.2.1.11 Chip Selects (CS[6:0])
      • 14.2.2 SDRAM Controller Signals
        • 14.2.2.1 SDRAM Row Address Strobe (SRAS)
        • 14.2.2.2 SDRAM Column Address Strobe (SCAS)
        • 14.2.2.3 SDRAM Write Enable (DRAMW)
        • 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0])
        • 14.2.2.5 SDRAM Clock Enable (SCKE)
      • 14.2.3 Clock and Reset Signals
        • 14.2.3.1 Reset In (RSTI)
        • 14.2.3.2 Reset Out (RSTO)
        • 14.2.3.3 EXTAL
        • 14.2.3.4 XTAL
        • 14.2.3.5 Clock Output (CLKOUT)
      • 14.2.4 Chip Configuration Signals
        • 14.2.4.1 RCON
        • 14.2.4.2 CLKMOD[1:0]
      • 14.2.5 External Interrupt Signals
        • 14.2.5.1 External Interrupts (IRQ[7:1])
      • 14.2.6 Ethernet Module Signals
        • 14.2.6.1 Management Data (EMDIO)
        • 14.2.6.2 Management Data Clock (EMDC)
        • 14.2.6.3 Transmit Clock (ETXCLK)
        • 14.2.6.4 Transmit Enable (ETXEN)
        • 14.2.6.5 Transmit Data 0 (ETXD0)
        • 14.2.6.6 Collision (ECOL)
        • 14.2.6.7 Receive Clock (ERXCLK)
        • 14.2.6.8 Receive Data Valid (ERXDV)
        • 14.2.6.9 Receive Data 0 (ERXD0)
        • 14.2.6.10 Carrier Receive Sense (ECRS)
        • 14.2.6.11 Transmit Data 1-3 (ETXD[3:1])
        • 14.2.6.12 Transmit Error (ETXER)
        • 14.2.6.13 Receive Data 1-3 (ERXD[3:1])
        • 14.2.6.14 Receive Error (ERXER)
      • 14.2.7 Queued Serial Peripheral Interface (QSPI) Signals
        • 14.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT)
        • 14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN)
        • 14.2.7.3 QSPI Serial Clock (QSPI_CLK)
        • 14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0])
      • 14.2.8 FlexCAN Signals
        • 14.2.8.1 FlexCAN Transmit (CANTX)
        • 14.2.8.2 FlexCAN Receive (CANRX)
      • 14.2.9 I2C Signals
        • 14.2.9.1 Serial Clock (SCL)
        • 14.2.9.2 Serial Data (SDA)
      • 14.2.10 UART Module Signals
        • 14.2.10.1 Transmit Serial Data Output (UTXD[2:0])
        • 14.2.10.2 Receive Serial Data Input (URXD[2:0])
        • 14.2.10.3 Clear-to-Send (UCTS[1:0])
        • 14.2.10.4 Request-to-Send (URTS[1:0])
      • 14.2.11 General Purpose Timer Signals
        • 14.2.11.1 GPTA[3:0]
        • 14.2.11.2 GPTB[3:0]
        • 14.2.11.3 External Clock Input (SYNCA/SYNCB)
      • 14.2.12 DMA Timer Signals
        • 14.2.12.1 DMA Timer 0 Input (DTIN0)
        • 14.2.12.2 DMA Timer 0 Output (DTOUT0)
        • 14.2.12.3 DMA Timer 1 Input (DTIN1)
        • 14.2.12.4 DMA Timer 1 Output (DTOUT1)
        • 14.2.12.5 DMA Timer 2 Input (DTIN2)
        • 14.2.12.6 DMA Timer 2 Output (DTOUT2)
        • 14.2.12.7 DMA Timer 3 Input (DTIN3)
        • 14.2.12.8 DMA Timer 3 Output (DTOUT3)
      • 14.2.13 Analog-to-Digital Converter Signals
        • 14.2.13.1 QADC Analog Input (AN0/ANW)
        • 14.2.13.2 QADC Analog Input (AN1/ANX)
        • 14.2.13.3 QADC Analog Input (AN2/ANY)
        • 14.2.13.4 QADC Analog Input (AN3/ANZ)
        • 14.2.13.5 QADC Analog Input (AN52/MA0)
        • 14.2.13.6 QADC Analog Input (AN53/MA1)
        • 14.2.13.7 QADC Analog Input (AN55/TRIG1)
        • 14.2.13.8 QADC Analog Input (AN56/TRIG2)
      • 14.2.14 Debug Support Signals
        • 14.2.14.1 JTAG_EN
        • 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)
        • 14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS)
        • 14.2.14.4 Development Serial Input/Test Data (DSI/TDI)
        • 14.2.14.5 Development Serial Output/Test Data (DSO/TDO)
        • 14.2.14.6 Test Clock (TCLK)
        • 14.2.14.7 Debug Data (DDATA[3:0])
        • 14.2.14.8 Processor Status Outputs (PST[3:0])
      • 14.2.15 Test Signals
        • 14.2.15.1 Test (TEST)
      • 14.2.16 Power and Reference Signals
        • 14.2.16.1 QADC Analog Reference (VRH, VRL)
        • 14.2.16.2 QADC Analog Supply (VDDA, VSSA)
        • 14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL)
        • 14.2.16.4 QADC Positive Supply (VDDH)
        • 14.2.16.5 Power for Flash Erase/Program (VPP)
        • 14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF)
        • 14.2.16.7 Standby Power (VSTBY)
        • 14.2.16.8 Positive Supply (VDD)
        • 14.2.16.9 Ground (VSS)
  • Chapter 15 Synchronous DRAM Controller Module
    • 15.1 Overview
      • 15.1.1 Definitions
      • 15.1.2 Block Diagram and Major Components
    • 15.2 SDRAM Controller Operation
      • 15.2.1 DRAM Controller Signals
      • 15.2.2 Memory Map for SDRAMC Registers
        • 15.2.2.1 DRAM Control Register (DCR)
        • 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)
        • 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1)
      • 15.2.3 General Synchronous Operation Guidelines
        • 15.2.3.1 Address Multiplexing
        • 15.2.3.2 SDRAM Byte Strobe Connections
        • 15.2.3.3 Interfacing Example
        • 15.2.3.4 Burst Page Mode
        • 15.2.3.5 Auto-Refresh Operation
        • 15.2.3.6 Self-Refresh Operation
      • 15.2.4 Initialization Sequence
        • 15.2.4.1 Mode Register Settings
    • 15.3 SDRAM Example
      • 15.3.1 SDRAM Interface Configuration
      • 15.3.2 DCR Initialization
      • 15.3.3 DACR Initialization
      • 15.3.4 DMR Initialization
      • 15.3.5 Mode Register Initialization
      • 15.3.6 Initialization Code
  • Chapter 16 DMA Controller Module
    • 16.1 Overview
      • 16.1.1 DMA Module Features
    • 16.2 DMA Request Control (DMAREQC)
    • 16.3 DMA Transfer Overview
    • 16.4 DMA Controller Module Programming Model
      • 16.4.1 Source Address Registers (SAR0-SAR3)
      • 16.4.2 Destination Address Registers (DAR0-DAR3)
      • 16.4.3 Byte Count Registers (BCR0-BCR3)
      • 16.4.4 DMA Control Registers (DCR0-DCR3)
      • 16.4.5 DMA Status Registers (DSR0-DSR3)
    • 16.5 DMA Controller Module Functional Description
      • 16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)
      • 16.5.2 Data Transfer Modes
        • 16.5.2.1 Dual-Address Transfers
      • 16.5.3 Channel Initialization and Startup
        • 16.5.3.1 Channel Prioritization
        • 16.5.3.2 Programming the DMA Controller Module
      • 16.5.4 Data Transfer
        • 16.5.4.1 Auto-Alignment
        • 16.5.4.2 Bandwidth Control
      • 16.5.5 Termination
  • Chapter 17 Fast Ethernet Controller (FEC)
    • 17.1 Introduction
      • 17.1.1 Overview
      • 17.1.2 Block Diagram
      • 17.1.3 Features
    • 17.2 Modes of Operation
      • 17.2.1 Full and Half Duplex Operation
      • 17.2.2 Interface Options
        • 17.2.2.1 10 Mbps and 100 Mbps MII Interface
        • 17.2.2.2 10 Mpbs 7-Wire Interface Operation
      • 17.2.3 Address Recognition Options
      • 17.2.4 Internal Loopback
    • 17.3 External Signal Description
    • 17.4 Memory Map/Register Definition
      • 17.4.1 MIB Block Counters Memory Map
      • 17.4.2 Ethernet Interrupt Event Register (EIR)
      • 17.4.3 Interrupt Mask Register (EIMR)
      • 17.4.4 Receive Descriptor Active Register (RDAR)
      • 17.4.5 Transmit Descriptor Active Register (TDAR)
      • 17.4.6 Ethernet Control Register (ECR)
      • 17.4.7 MII Management Frame Register (MMFR)
      • 17.4.8 MII Speed Control Register (MSCR)
      • 17.4.9 MIB Control Register (MIBC)
      • 17.4.10 Receive Control Register (RCR)
      • 17.4.11 Transmit Control Register (TCR)
      • 17.4.12 Physical Address Lower Register (PALR)
      • 17.4.13 Physical Address Upper Register (PAUR)
      • 17.4.14 Opcode/Pause Duration Register (OPD)
      • 17.4.15 Descriptor Individual Upper Address Register (IAUR)
      • 17.4.16 Descriptor Individual Lower Address Register (IALR)
      • 17.4.17 Descriptor Group Upper Address Register (GAUR)
      • 17.4.18 Descriptor Group Lower Address Register (GALR)
      • 17.4.19 Transmit FIFO Watermark Register (TFWR)
      • 17.4.20 FIFO Receive Bound Register (FRBR)
      • 17.4.21 FIFO Receive Start Register (FRSR)
      • 17.4.22 Receive Descriptor Ring Start Register (ERDSR)
      • 17.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)
      • 17.4.24 Receive Buffer Size Register (EMRBR)
    • 17.5 Functional Description
      • 17.5.1 Buffer Descriptors
        • 17.5.1.1 Driver/DMA Operation with Buffer Descriptors
          • 17.5.1.1.1 Driver/DMA Operation with Transmit BDs
          • 17.5.1.1.2 Driver/DMA Operation with Receive BDs
        • 17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD)
        • 17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD)
      • 17.5.2 Initialization Sequence
        • 17.5.2.1 Hardware Controlled Initialization
      • 17.5.3 User Initialization (Prior to Setting ECR[ETHER_EN])
      • 17.5.4 Microcontroller Initialization
      • 17.5.5 User Initialization (After Setting ECR[ETHER_EN])
      • 17.5.6 Network Interface Options
      • 17.5.7 FEC Frame Transmission
        • 17.5.7.1 Duplicate Frame Transmission
      • 17.5.8 FEC Frame Reception
      • 17.5.9 Ethernet Address Recognition
      • 17.5.10 Hash Algorithm
      • 17.5.11 Full Duplex Flow Control
      • 17.5.12 Inter-Packet Gap (IPG) Time
      • 17.5.13 Collision Managing
      • 17.5.14 MII Internal and External Loopback
      • 17.5.15 Ethernet Error-Managing Procedure
        • 17.5.15.1 Transmission Errors
          • 17.5.15.1.1 Transmitter Underrun
          • 17.5.15.1.2 Retransmission Attempts Limit Expired
          • 17.5.15.1.3 Late Collision
          • 17.5.15.1.4 Heartbeat
        • 17.5.15.2 Reception Errors
          • 17.5.15.2.1 Overrun Error
          • 17.5.15.2.2 Non-Octet Error (Dribbling Bits)
          • 17.5.15.2.3 CRC Error
          • 17.5.15.2.4 Frame Length Violation
          • 17.5.15.2.5 Truncation
  • Chapter 18 Watchdog Timer Module
    • 18.1 Introduction
    • 18.2 Low-Power Mode Operation
    • 18.3 Block Diagram
    • 18.4 Signals
    • 18.5 Memory Map and Registers
      • 18.5.1 Memory Map
      • 18.5.2 Registers
        • 18.5.2.1 Watchdog Control Register (WCR)
        • 18.5.2.2 Watchdog Modulus Register (WMR)
        • 18.5.2.3 Watchdog Count Register (WCNTR)
        • 18.5.2.4 Watchdog Service Register (WSR)
  • Chapter 19 Programmable Interrupt Timers (PIT0-PIT3)
    • 19.1 Introduction
      • 19.1.1 Overview
      • 19.1.2 Block Diagram
      • 19.1.3 Low-Power Mode Operation
    • 19.2 Memory Map/Register Definition
      • 19.2.1 PIT Control and Status Register (PCSRn)
      • 19.2.2 PIT Modulus Register (PMRn)
      • 19.2.3 PIT Count Register (PCNTRn)
    • 19.3 Functional Description
      • 19.3.1 Set-and-Forget Timer Operation
      • 19.3.2 Free-Running Timer Operation
      • 19.3.3 Timeout Specifications
      • 19.3.4 Interrupt Operation
  • Chapter 20 General Purpose Timer Modules (GPTA and GPTB)
    • 20.1 Features
    • 20.2 Block Diagram
    • 20.3 Low-Power Mode Operation
    • 20.4 Signal Description
      • 20.4.1 GPTn[2:0]
      • 20.4.2 GPTn3
      • 20.4.3 SYNCn
    • 20.5 Memory Map and Registers
      • 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)
      • 20.5.2 GPT Compare Force Register (GPCFORC)
      • 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)
      • 20.5.4 GPT Output Compare 3 Data Register (GPTOC3D)
      • 20.5.5 GPT Counter Register (GPTCNT)
      • 20.5.6 GPT System Control Register 1 (GPTSCR1)
      • 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)
      • 20.5.8 GPT Control Register 1 (GPTCTL1)
      • 20.5.9 GPT Control Register 2 (GPTCTL2)
      • 20.5.10 GPT Interrupt Enable Register (GPTIE)
      • 20.5.11 GPT System Control Register 2 (GPTSCR2)
      • 20.5.12 GPT Flag Register 1 (GPTFLG1)
      • 20.5.13 GPT Flag Register 2 (GPTFLG2)
      • 20.5.14 GPT Channel Registers (GPTCn)
      • 20.5.15 Pulse Accumulator Control Register (GPTPACTL)
      • 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)
      • 20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
      • 20.5.18 GPT Port Data Register (GPTPORT)
      • 20.5.19 GPT Port Data Direction Register (GPTDDR)
    • 20.6 Functional Description
      • 20.6.1 Prescaler
      • 20.6.2 Input Capture
      • 20.6.3 Output Compare
      • 20.6.4 Pulse Accumulator
      • 20.6.5 Event Counter Mode
      • 20.6.6 Gated Time Accumulation Mode
      • 20.6.7 General-Purpose I/O Ports
    • 20.7 Reset
    • 20.8 Interrupts
      • 20.8.1 GPT Channel Interrupts (CnF)
      • 20.8.2 Pulse Accumulator Overflow (PAOVF)
      • 20.8.3 Pulse Accumulator Input (PAIF)
      • 20.8.4 Timer Overflow (TOF)
  • Chapter 21 DMA Timers (DTIM0-DTIM3)
    • 21.1 Introduction
      • 21.1.1 Overview
      • 21.1.2 Features
    • 21.2 Memory Map/Register Definition
      • 21.2.1 DMA Timer Mode Registers (DTMRn)
      • 21.2.2 DMA Timer Extended Mode Registers (DTXMRn)
      • 21.2.3 DMA Timer Event Registers (DTERn)
      • 21.2.4 DMA Timer Reference Registers (DTRRn)
      • 21.2.5 DMA Timer Capture Registers (DTCRn)
      • 21.2.6 DMA Timer Counters (DTCNn)
    • 21.3 Functional Description
      • 21.3.1 Prescaler
      • 21.3.2 Capture Mode
      • 21.3.3 Reference Compare
      • 21.3.4 Output Mode
    • 21.4 Initialization/Application Information
      • 21.4.1 Code Example
      • 21.4.2 Calculating Time-Out Values
  • Chapter 22 Queued Serial Peripheral Interface (QSPI)
    • 22.1 Introduction
      • 22.1.1 Block Diagram
      • 22.1.2 Overview
      • 22.1.3 Features
      • 22.1.4 Modes of Operation
    • 22.2 External Signal Description
    • 22.3 Memory Map/Register Definition
      • 22.3.1 QSPI Mode Register (QMR)
      • 22.3.2 QSPI Delay Register (QDLYR)
      • 22.3.3 QSPI Wrap Register (QWR)
      • 22.3.4 QSPI Interrupt Register (QIR)
      • 22.3.5 QSPI Address Register (QAR)
      • 22.3.6 QSPI Data Register (QDR)
      • 22.3.7 Command RAM Registers (QCR0-QCR15)
    • 22.4 Functional Description
      • 22.4.1 QSPI RAM
        • 22.4.1.1 Receive RAM
        • 22.4.1.2 Transmit RAM
        • 22.4.1.3 Command RAM
      • 22.4.2 Baud Rate Selection
      • 22.4.3 Transfer Delays
      • 22.4.4 Transfer Length
      • 22.4.5 Data Transfer
    • 22.5 Initialization/Application Information
  • Chapter 23 UART Modules
    • 23.1 Introduction
      • 23.1.1 Overview
      • 23.1.2 Features
    • 23.2 External Signal Description
    • 23.3 Memory Map/Register Definition
      • 23.3.1 UART Mode Registers 1 (UMR1n)
      • 23.3.2 UART Mode Register 2 (UMR2n)
      • 23.3.3 UART Status Registers (USRn)
      • 23.3.4 UART Clock Select Registers (UCSRn)
      • 23.3.5 UART Command Registers (UCRn)
      • 23.3.6 UART Receive Buffers (URBn)
      • 23.3.7 UART Transmit Buffers (UTBn)
      • 23.3.8 UART Input Port Change Registers (UIPCRn)
      • 23.3.9 UART Auxiliary Control Register (UACRn)
      • 23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
      • 23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
      • 23.3.12 UART Input Port Register (UIPn)
      • 23.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
    • 23.4 Functional Description
      • 23.4.1 Transmitter/Receiver Clock Source
        • 23.4.1.1 Programmable Divider
        • 23.4.1.2 Calculating Baud Rates
          • 23.4.1.2.1 Internal Bus Clock Baud Rates
          • 23.4.1.2.2 External Clock
      • 23.4.2 Transmitter and Receiver Operating Modes
        • 23.4.2.1 Transmitter
        • 23.4.2.2 Receiver
        • 23.4.2.3 FIFO
      • 23.4.3 Looping Modes
        • 23.4.3.1 Automatic Echo Mode
        • 23.4.3.2 Local Loopback Mode
        • 23.4.3.3 Remote Loopback Mode
      • 23.4.4 Multidrop Mode
      • 23.4.5 Bus Operation
        • 23.4.5.1 Read Cycles
        • 23.4.5.2 Write Cycles
    • 23.5 Initialization/Application Information
      • 23.5.1 Interrupt and DMA Request Initialization
        • 23.5.1.1 Setting up the UART to Generate Core Interrupts
        • 23.5.1.2 Setting up the UART to Request DMA Service
      • 23.5.2 UART Module Initialization Sequence
  • Chapter 24 I2C Interface
    • 24.1 Introduction
      • 24.1.1 Block Diagram
      • 24.1.2 Overview
      • 24.1.3 Features
    • 24.2 Memory Map/Register Definition
      • 24.2.1 I2C Address Register (I2ADR)
      • 24.2.2 I2C Frequency Divider Register (I2FDR)
      • 24.2.3 I2C Control Register (I2CR)
      • 24.2.4 I2C Status Register (I2SR)
      • 24.2.5 I2C Data I/O Register (I2DR)
    • 24.3 Functional Description
      • 24.3.1 START Signal
      • 24.3.2 Slave Address Transmission
      • 24.3.3 Data Transfer
      • 24.3.4 Acknowledge
      • 24.3.5 STOP Signal
      • 24.3.6 Repeated START
      • 24.3.7 Clock Synchronization and Arbitration
      • 24.3.8 Handshaking and Clock Stretching
    • 24.4 Initialization/Application Information
      • 24.4.1 Initialization Sequence
      • 24.4.2 Generation of START
      • 24.4.3 Post-Transfer Software Response
      • 24.4.4 Generation of STOP
      • 24.4.5 Generation of Repeated START
      • 24.4.6 Slave Mode
      • 24.4.7 Arbitration Lost
  • Chapter 25 FlexCAN
    • 25.1 Features
      • 25.1.1 FlexCAN Memory Map
      • 25.1.2 External Signals
    • 25.2 The CAN System
    • 25.3 Message Buffers
      • 25.3.1 Message Buffer Structure
        • 25.3.1.1 Common Fields for Extended and Standard Format Frames
        • 25.3.1.2 Fields for Extended Format Frames
        • 25.3.1.3 Fields for Standard Format Frames
      • 25.3.2 Message Buffer Memory Map
    • 25.4 Functional Overview
      • 25.4.1 Transmit Process
      • 25.4.2 Receive Process
        • 25.4.2.1 Self-Received Frames
      • 25.4.3 Message Buffer Handling
        • 25.4.3.1 Serial Message Buffers (SMBs)
        • 25.4.3.2 Transmit Message Buffer Deactivation
        • 25.4.3.3 Receive Message Buffer Deactivation
        • 25.4.3.4 Locking and Releasing Message Buffers
      • 25.4.4 Remote Frames
      • 25.4.5 Overload Frames
      • 25.4.6 Time Stamp
      • 25.4.7 Listen-Only Mode
      • 25.4.8 Bit Timing
        • 25.4.8.1 Configuring the FlexCAN Bit Timing
      • 25.4.9 FlexCAN Error Counters
      • 25.4.10 FlexCAN Initialization Sequence
      • 25.4.11 Special Operating Modes
        • 25.4.11.1 Debug Mode
        • 25.4.11.2 Low-Power Stop Mode for Power Saving
        • 25.4.11.3 Auto-Power Save Mode
      • 25.4.12 Interrupts
    • 25.5 Programmer’s Model
      • 25.5.1 CAN Module Configuration Register (CANMCR)
      • 25.5.2 FlexCAN Control Register 0 (CANCTRL0)
      • 25.5.3 FlexCAN Control Register 1 (CANCTRL1)
      • 25.5.4 Prescaler Divide Register (PRESDIV)
      • 25.5.5 FlexCAN Control Register 2 (CANCTRL2)
      • 25.5.6 Free Running Timer (TIMER)
      • 25.5.7 Rx Mask Registers
        • 25.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK)
      • 25.5.8 FlexCAN Error and Status Register (ESTAT)
      • 25.5.9 Interrupt Mask Register (IMASK)
      • 25.5.10 Interrupt Flag Register (IFLAG)
      • 25.5.11 FlexCAN Receive Error Counter (RXECTR)
      • 25.5.12 FlexCAN Transmit Error Counter (TXECTR)
  • Chapter 26 General Purpose I/O Module
    • 26.1 Introduction
      • 26.1.1 Overview
      • 26.1.2 Features
      • 26.1.3 Modes of Operation
    • 26.2 External Signal Description
    • 26.3 Memory Map/Register Definition
      • 26.3.1 Register Overview
      • 26.3.2 Register Descriptions
        • 26.3.2.1 Port Output Data Registers (PORTn)
        • 26.3.2.2 Port Data Direction Registers (DDRn)
        • 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn)
        • 26.3.2.4 Port Clear Output Data Registers (CLRn)
        • 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)
        • 26.3.2.6 Port E Pin Assignment Register (PEPAR)
        • 26.3.2.7 Port F Pin Assignment Register (PFPAR)
        • 26.3.2.8 Port J Pin Assignment Register (PJPAR)
        • 26.3.2.9 Port SD Pin Assignment Register (PSDPAR)
        • 26.3.2.10 Port AS Pin Assignment Register (PASPAR)
        • 26.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR)
        • 26.3.2.12 Port QS Pin Assignment Register (PQSPAR)
        • 26.3.2.13 Port TC Pin Assignment Register (PTCPAR)
        • 26.3.2.14 Port TD Pin Assignment Register (PTDPAR)
        • 26.3.2.15 Port UA Pin Assignment Register (PUAPAR)
    • 26.4 Functional Description
      • 26.4.1 Overview
      • 26.4.2 Port Digital I/O Timing
    • 26.5 Initialization/Application Information
  • Chapter 27 Chip Configuration Module (CCM)
    • 27.1 Features
    • 27.2 Modes of Operation
      • 27.2.1 Master Mode
      • 27.2.2 Single-Chip Mode
    • 27.3 Block Diagram
    • 27.4 Signal Descriptions
      • 27.4.1 RCON
      • 27.4.2 CLKMOD[1:0]
      • 27.4.3 D[26:24, 21, 19:16] (Reset Configuration Override)
    • 27.5 Memory Map and Registers
      • 27.5.1 Programming Model
      • 27.5.2 Memory Map
      • 27.5.3 Register Descriptions
        • 27.5.3.1 Chip Configuration Register (CCR)
        • 27.5.3.2 Reset Configuration Register (RCON)
        • 27.5.3.3 Chip Identification Register (CIR)
    • 27.6 Functional Description
      • 27.6.1 Reset Configuration
      • 27.6.2 Chip Mode Selection
      • 27.6.3 Boot Device Selection
      • 27.6.4 Output Pad Strength Configuration
      • 27.6.5 Clock Mode Selection
      • 27.6.6 Chip Select Configuration
    • 27.7 Reset
    • 27.8 Interrupts
  • Chapter 28 Queued Analog-to-Digital Converter (QADC)
    • 28.1 Features
    • 28.2 Block Diagram
    • 28.3 Modes of Operation
      • 28.3.1 Debug Mode
      • 28.3.2 Stop Mode
    • 28.4 Signals
      • 28.4.1 Port QA Signal Functions
        • 28.4.1.1 Port QA Analog Input Signals
        • 28.4.1.2 Port QA Digital Input/Output Signals
      • 28.4.2 Port QB Signal Functions
        • 28.4.2.1 Port QB Analog Input Signals
        • 28.4.2.2 Port QB Digital I/O Signals
      • 28.4.3 External Trigger Input Signals
      • 28.4.4 Multiplexed Address Output Signals
      • 28.4.5 Multiplexed Analog Input Signals
      • 28.4.6 Voltage Reference Signals
      • 28.4.7 Dedicated Analog Supply Signals
      • 28.4.8 Dedicated Digital I/O Port Supply Signal
    • 28.5 Memory Map
    • 28.6 Register Descriptions
      • 28.6.1 QADC Module Configuration Register (QADCMCR)
      • 28.6.2 QADC Test Register (QADCTEST)
      • 28.6.3 Port Data Registers (PORTQA & PORTQB)
      • 28.6.4 Port QA and QB Data Direction Register (DDRQA & DDRQB)
      • 28.6.5 Control Registers
        • 28.6.5.1 QADC Control Register 0 (QACR0)
        • 28.6.5.2 QADC Control Register 1 (QACR1)
        • 28.6.5.3 QADC Control Register 2 (QACR2)
      • 28.6.6 Status Registers
        • 28.6.6.1 QADC Status Register 0 (QASR0)
        • 28.6.6.2 QADC Status Register 1 (QASR1)
      • 28.6.7 Conversion Command Word Table (CCW)
      • 28.6.8 Result Registers
        • 28.6.8.1 Right-Justified Unsigned Result Register (RJURR)
        • 28.6.8.2 Left-Justified Signed Result Register (LJSRR)
        • 28.6.8.3 Left-Justified Unsigned Result Register (LJURR)
    • 28.7 Functional Description
      • 28.7.1 Result Coherency
      • 28.7.2 External Multiplexing
        • 28.7.2.1 External Multiplexing Operation
        • 28.7.2.2 Module Version Options
      • 28.7.3 Analog Subsystem
        • 28.7.3.1 Analog-to-Digital Converter Operation
        • 28.7.3.2 Conversion Cycle Times
        • 28.7.3.3 Channel Decode and Multiplexer
        • 28.7.3.4 Sample Buffer
        • 28.7.3.5 Comparator
        • 28.7.3.6 Bias
        • 28.7.3.7 Successive Approximation Register (SAR)
        • 28.7.3.8 State Machine
    • 28.8 Digital Control Subsystem
      • 28.8.1 Queue Priority Timing Examples
        • 28.8.1.1 Queue Priority
        • 28.8.1.2 Queue Priority Schemes
      • 28.8.2 Boundary Conditions
      • 28.8.3 Scan Modes
      • 28.8.4 Disabled Mode
      • 28.8.5 Reserved Mode
      • 28.8.6 Single-Scan Modes
        • 28.8.6.1 Software-Initiated Single-Scan Mode
        • 28.8.6.2 Externally Triggered Single-Scan Mode
        • 28.8.6.3 Externally Gated Single-Scan Mode
        • 28.8.6.4 Interval Timer Single-Scan Mode
      • 28.8.7 Continuous-Scan Modes
        • 28.8.7.1 Software-Initiated Continuous-Scan Mode
        • 28.8.7.2 Externally Triggered Continuous-Scan Mode
        • 28.8.7.3 Externally Gated Continuous-Scan Mode
        • 28.8.7.4 Periodic Timer Continuous-Scan Mode
      • 28.8.8 QADC Clock (QCLK) Generation
      • 28.8.9 Periodic/Interval Timer
      • 28.8.10 Conversion Command Word Table
      • 28.8.11 Result Word Table
    • 28.9 Signal Connection Considerations
      • 28.9.1 Analog Reference Signals
      • 28.9.2 Analog Power Signals
      • 28.9.3 Conversion Timing Schemes
      • 28.9.4 Analog Supply Filtering and Grounding
      • 28.9.5 Accommodating Positive/Negative Stress Conditions
      • 28.9.6 Analog Input Considerations
      • 28.9.7 Analog Input Pins
        • 28.9.7.1 Settling Time for the External Circuit
        • 28.9.7.2 Error Resulting from Leakage
    • 28.10 Interrupts
      • 28.10.1 Interrupt Operation
      • 28.10.2 Interrupt Sources
  • Chapter 29 Reset Controller Module
    • 29.1 Features
    • 29.2 Block Diagram
    • 29.3 Signals
      • 29.3.1 RSTI
      • 29.3.2 RSTO
    • 29.4 Memory Map and Registers
      • 29.4.1 Reset Control Register (RCR)
      • 29.4.2 Reset Status Register (RSR)
    • 29.5 Functional Description
      • 29.5.1 Reset Sources
        • 29.5.1.1 Power-On Reset
        • 29.5.1.2 External Reset
        • 29.5.1.3 Watchdog Timer Reset
        • 29.5.1.4 Loss-of-Clock Reset
        • 29.5.1.5 Loss-of-Lock Reset
        • 29.5.1.6 Software Reset
        • 29.5.1.7 LVD Reset
      • 29.5.2 Reset Control Flow
        • 29.5.2.1 Synchronous Reset Requests
        • 29.5.2.2 Internal Reset Request
        • 29.5.2.3 Power-On Reset/Low-Voltage Detect Reset
      • 29.5.3 Concurrent Resets
        • 29.5.3.1 Reset Flow
        • 29.5.3.2 Reset Status Flags
  • Chapter 30 Debug Support
    • 30.1 Overview
    • 30.2 Signal Description
    • 30.3 Real-Time Trace Support
      • 30.3.1 Begin Execution of Taken Branch (PST = 0x5)
    • 30.4 Programming Model
      • 30.4.1 Revision A Shared Debug Resources
      • 30.4.2 Address Attribute Trigger Register (AATR)
      • 30.4.3 Address Breakpoint Registers (ABLR, ABHR)
      • 30.4.4 Configuration/Status Register (CSR)
      • 30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)
      • 30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)
      • 30.4.7 Trigger Definition Register (TDR)
    • 30.5 Background Debug Mode (BDM)
      • 30.5.1 CPU Halt
      • 30.5.2 BDM Serial Interface
        • 30.5.2.1 Receive Packet Format
        • 30.5.2.2 Transmit Packet Format
      • 30.5.3 BDM Command Set
        • 30.5.3.1 ColdFire BDM Command Format
          • 30.5.3.1.1 Extension Words as Required
        • 30.5.3.2 Command Sequence Diagrams
        • 30.5.3.3 Command Set Descriptions
          • 30.5.3.3.1 Read A/D Register (rareg/rdreg)
          • 30.5.3.3.2 Write A/D Register (wareg/wdreg)
          • 30.5.3.3.3 Read Memory Location (read)
          • 30.5.3.3.4 Write Memory Location (write)
          • 30.5.3.3.5 Dump Memory Block (dump)
          • 30.5.3.3.6 Fill Memory Block (fill)
          • 30.5.3.3.7 Resume Execution (go)
          • 30.5.3.3.8 No Operation (nop)
          • 30.5.3.3.9 Read Control Register (rcreg)
          • 30.5.3.3.10 Write Control Register (wcreg)
          • 30.5.3.3.11 Read Debug Module Register (rdmreg)
          • 30.5.3.3.12 Write Debug Module Register (wdmreg)
    • 30.6 Real-Time Debug Support
      • 30.6.1 Theory of Operation
        • 30.6.1.1 Emulator Mode
      • 30.6.2 Concurrent BDM and Processor Operation
    • 30.7 Processor Status, DDATA Definition
      • 30.7.1 User Instruction Set
      • 30.7.2 Supervisor Instruction Set
    • 30.8 Freescale-Recommended BDM Pinout
  • Chapter 31 IEEE 1149.1 Test Access Port (JTAG)
    • 31.1 Features
    • 31.2 Modes of Operation
    • 31.3 External Signal Description
      • 31.3.1 Detailed Signal Description
        • 31.3.1.1 JTAG_EN - JTAG Enable
        • 31.3.1.2 TCLK - Test Clock Input
        • 31.3.1.3 TMS/BKPT - Test Mode Select / Breakpoint
        • 31.3.1.4 TDI/DSI - Test Data Input / Development Serial Input
        • 31.3.1.5 TRST/DSCLK - Test Reset / Development Serial Clock
        • 31.3.1.6 TDO/DSO - Test Data Output / Development Serial Output
    • 31.4 Memory Map/Register Definition
      • 31.4.1 Memory Map
      • 31.4.2 Register Descriptions
        • 31.4.2.1 Instruction Shift Register (IR)
        • 31.4.2.2 IDCODE Register
        • 31.4.2.3 Bypass Register
        • 31.4.2.4 JTAG_CFM_CLKDIV Register
        • 31.4.2.5 TEST_CTRL Register
        • 31.4.2.6 Boundary Scan Register
    • 31.5 Functional Description
      • 31.5.1 JTAG Module
      • 31.5.2 TAP Controller
      • 31.5.3 JTAG Instructions
        • 31.5.3.1 External Test Instruction (EXTEST)
        • 31.5.3.2 IDCODE Instruction
        • 31.5.3.3 SAMPLE/PRELOAD Instruction
        • 31.5.3.4 TEST_LEAKAGE Instruction
        • 31.5.3.5 ENABLE_TEST_CTRL Instruction
        • 31.5.3.6 HIGHZ Instruction
        • 31.5.3.7 LOCKOUT_RECOVERY Instruction
        • 31.5.3.8 CLAMP Instruction
        • 31.5.3.9 BYPASS Instruction
    • 31.6 Initialization/Application Information
      • 31.6.1 Restrictions
      • 31.6.2 Nonscan Chain Operation
  • Chapter 32 Mechanical Data
    • 32.1 Pinout
    • 32.2 Ordering Information
  • Chapter 33 Electrical Characteristics
    • 33.1 Maximum Ratings
    • 33.2 Thermal Characteristics
    • 33.3 DC Electrical Specifications
    • 33.4 Power Consumption Specifications
    • 33.5 Phase Lock Loop Electrical Specifications
    • 33.6 QADC Electrical Characteristics
    • 33.7 Flash Memory Characteristics
    • 33.8 External Interface Timing Characteristics
    • 33.9 Processor Bus Output Timing Specifications
    • 33.10 General Purpose I/O Timing
    • 33.11 Reset and Configuration Override Timing
    • 33.12 I2C Input/Output Timing Specifications
    • 33.13 Fast Ethernet AC Timing Specifications
      • 33.13.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
      • 33.13.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
      • 33.13.3 MII Async Inputs Signal Timing (ECRS and ECOL)
      • 33.13.4 MII Serial Management Channel Timing (EMDIO and EMDC)
    • 33.14 DMA Timer Module AC Timing Specifications
    • 33.15 QSPI Electrical Specifications
    • 33.16 JTAG and Boundary Scan Timing
    • 33.17 Debug AC Timing Specifications
  • Appendix A Register Memory Map
  • Appendix B Revision History
    • B.1 Changes Between Rev. 0 and Rev. 0.1
    • B.2 Changes Between Rev. 0.1 and Rev. 1
    • B.3 Changes Between Rev. 1 and Rev. 2
    • B.4 Changes Between Rev. 2 and Rev. 2.1
    • B.5 Changes Between Rev. 2.1 and Rev. 2.2
    • B.6 Changes Between Rev. 2.2 and Rev. 2.3
    • B.7 Changes Between Rev. 2.3 and Rev. 3
      • A
      • B
      • C
      • D
      • E
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