Document Outline

• Overview
  • 1.1 Introduction
    • 1.1.1 Manual Organization
    • 1.1.2 Manual Conventions
      • Example11 Sample Code Listing
• Table11 High True / Low True Signal Conventions
  • 1.2 DSP56012 Features
• Table12 DSP56012 Internal Memory Configurations
  • 1.3 DSP56012 Architectural Overview
• Figure11 DSP56012 Block Diagram
  • 1.3.1 Peripheral Modules
  • 1.3.2 DSP Core Processor
    • 1.3.2.1 Data Arithmetic and Logic Unit (Data ALU)
    • 1.3.2.2 Address Generation Unit (AGU)
    • 1.3.2.3 Program Control Unit
    • 1.3.2.4 Data Buses
    • 1.3.2.5 Address Buses
    • 1.3.2.6 Phase Lock Loop (PLL)
    • 1.3.2.7 On-Chip Emulation (OnCE) Port
  • 1.3.3 Memories
    • 1.3.3.1 Program Memory
• Table13 Interrupt Starting Addresses and Sources (Continued)
  • 1.3.3.2 X Data Memory
  • 1.3.3.3 Y Data Memory
  • 1.3.3.4 On-Chip Memory Configuration Bits
• Table14 Internal Memory Configurations 
  • 1.3.3.5 Memory Configuration Bits
  • 1.3.3.6 External Memory
  • 1.3.3.7 Bootstrap ROM
  • 1.3.3.8 Reserved Memory Spaces
  • 1.3.4 Input/Output
• Table15 On-chip Peripheral Memory Map (Continued)
  • 1.3.4.1 Parallel Host Interface (HI)
  • 1.3.4.2 Serial Host Interface (SHI)
  • 1.3.4.3 Serial Audio Interface (SAI)
  • 1.3.4.4 General Purpose I/O
  • 1.3.4.5 Digital Audio Transmitter (DAX)
• Signal Descriptions
  • 2.1 Signal Groupings
• Table21 DSP56012 Functional Signal Groupings
• Figure21 DSP56012 Signals
  • 2.2 Power
• Table22 Power Inputs
  • 2.3 Ground
• Table23 Grounds
  • 2.4 Phase Lock Loop (PLL)
• Table24 Phase Lock Loop Signals
  • 2.5 Interrupt and Mode Control
• Table25 Interrupt and Mode Control (Continued)
  • 2.6 Host Interface (HI)
• Table26 Host Interface (Continued)
  • 2.7 Serial Host Interface (SHI)
• Table27 Serial Host Interface (SHI) Signals (Continued)
  • 2.8 Serial Audio Interface (SAI)
    • 2.8.1 SAI Receive Section
• Table28 Serial Audio Interface (SAI) Receive Signals
  • 2.8.2 SAI Transmit Section
• Table29 Serial Audio Interface (SAI) Transmit Signals
  • 2.9 General Purpose Input/Output (GPIO)
• Table210 General Purpose I/O (GPIO) Signals
  • 2.10 Digital Audio Interface (DAX)
• Table211 Digital Audio Interface (DAX) Signals
  • 2.11 OnCE Port
• Table212 On-Chip Emulation Port (OnCE) Signals (Continued)
• Memory, Operating Modes, and Interrupts
  • 3.1 Introduction
• Table31 Internal Memory Configurations
  • 3.2 DSP56012 Data and Program Memory
    • 3.2.1 X and Y Data ROM
    • 3.2.2 Bootstrap ROM
  • 3.3 DSP56012 Data and Program Memory Maps
    • 3.3.1 Reserved Memory Spaces
• Figure31 Memory Maps for PEA = 0, PEB = 0
• Figure32 Memory Maps for PEA = 1, PEB = 0
• Figure33 Memory Maps for PEA = 0, PEB = 1
• Figure34 Memory Maps for PEA = 1, PEB = 1
  • 3.3.2 Dynamic Switch of Memory Configurations
  • 3.3.3 Internal I/O Memory Map
• Table32 Internal I/O Memory Map (Continued)
  • 3.4 Operating Mode Register (OMR)
• Figure35 Operating Mode Register (OMR)
  • 3.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0
  • 3.4.2 Program RAM Enable A and Program RAM Enable B (PEA and PEB)—Bits 2 and 3
  • 3.4.3 Stop Delay (SD)—Bit 6
  • 3.5 Operating Modes
• Table33 Operating Modes 
  • 3.6 Interrupt Priority Register
• Figure36 Interrupt Priority Register (Addr X:$FFFF)
• Table34 Interrupt Priorities (Continued)
• Table35 Interrupt Vectors (Continued)
  • 3.7 Phase Lock Loop (PLL) Configuration
• Figure37 PLL Configuration
  • 3.8 Operation on Hardware Reset
• Parallel Host Interface
  • 4.1 Introduction
• Figure41 Port B Interface
  • 4.2 Port B Configuration
• Figure42 Parallel Port B Registers
• Figure43 Port B GPIO Signals and Registers
• Figure44 Port B I/O Pin Control Logic
  • 4.2.1 Port B Control (PBC) Register
  • 4.2.2 Port B Data Direction Register (PBDDR)
  • 4.2.3 Port B Data (PBD) Register
  • 4.3 Programming the GPIO
• Figure45 Instructions to Write/Read Parallel Data with Port B
• Figure46 I/O Port B Configuration
  • 4.4 Host Interface (HI)
    • 4.4.1 HI Features
    • 4.4.2 HI Block Diagram
• Figure47 HI Block Diagram
  • 4.4.3 HI—DSP Viewpoint
  • 4.4.4 Programming Model—DSP Viewpoint
• Figure48 HI Programming Model–DSP Viewpoint
  • 4.4.4.1 HI Control Register (HCR)
    • 4.4.4.1.1 HCR HI Receive Interrupt Enable (HRIE)—Bit 0
    • 4.4.4.1.2 HCR HI Transmit Interrupt Enable (HTIE)—Bit 1
    • 4.4.4.1.3 HCR HI Command Interrupt Enable (HCIE)—Bit 2
    • 4.4.4.1.4 HCR HI Flag 2 (HF2)—Bit 3
    • 4.4.4.1.5 HCR HI Flag 3 (HF3)—Bit 4
    • 4.4.4.1.6 HCR Reserved—Bits 5, 6, and 7
  • 4.4.4.2 HI Status Register (HSR)
    • 4.4.4.2.1 HSR HI Receive Data Full (HRDF)—Bit 0
    • 4.4.4.2.2 HSR HI Transmit Data Empty (HTDE)—Bit 1
    • 4.4.4.2.3 HSR HI Command Pending (HCP)—Bit 2
    • 4.4.4.2.4 HSR HI Flag 0 (HF0)—Bit 3
    • 4.4.4.2.5 HSR HI Flag 1 (HF1)—Bit 4
• Figure49 HI Flag Operation
  • 4.4.4.2.6 HSR Reserved—Bits 5 and 6
  • 4.4.4.2.7 HSR DMA Status (DMA)—Bit 7
  • 4.4.4.3 HI Receive Data Register (HORX)
  • 4.4.4.4 HI Transmit Data Register (HOTX)
  • 4.4.4.5 Register Contents After Reset
• Table41 HI Registers after Reset—DSP CPU Side (Continued)
  • 4.4.4.6 DSP Interrupts
  • 4.4.4.7 HI Usage Considerations—DSP Side
  • 4.4.5 HI—Host Processor Viewpoint
    • 4.4.5.1 Programming Model—Host Processor Viewpoint
    • 4.4.5.2 Host Command
• Figure410 Host Processor Programming Model–Host Side
• Figure411 HI Register Map
  • 4.4.5.3 Interrupt Control Register (ICR)
    • 4.4.5.3.1 ICR Receive Request Enable (RREQ)—Bit 0
    • 4.4.5.3.2 ICR Transmit Request Enable (TREQ)—Bit 1
• Table42 HOREQ Pin Definition
  • 4.4.5.3.3 ICR Reserved—Bit 2
  • 4.4.5.3.4 ICR HI Flag 0 (HF0)—Bit 3
• Figure412 HSR and HCR Operation
  • 4.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 4
  • 4.4.5.3.6 ICR HI Mode Control (HM1 and HM0)—Bits 5 and 6
• Table43 HI Mode Bit Definition 
  • 4.4.5.3.7 ICR Initialize Bit (INIT)—Bit 7
  • 4.4.5.4 HI Initialization
• Table44 HOREQ Pin Definition 
  • 4.4.5.5 Command Vector Register (CVR)
    • 4.4.5.5.1 CVR HI Vector (HV)—Bits 0–5
• Figure413 Command Vector Register
  • 4.4.5.5.2 CVR Reserved—Bit 6
  • 4.4.5.5.3 CVR Host Command (HC)—Bit 7
  • 4.4.5.6 Interrupt Status Register (ISR)
    • 4.4.5.6.1 ISR Receive Data Register Full (RXDF)—Bit 0
    • 4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1
    • 4.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 2
    • 4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only)
    • 4.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only)
    • 4.4.5.6.6 ISR Reserved—Bit 5
    • 4.4.5.6.7 ISR DMA Status (DMA)—Bit 6
    • 4.4.5.6.8 ISR Host Request (HOREQ)—Bit 7
  • 4.4.5.7 Interrupt Vector Register (IVR)
  • 4.4.5.8 Receive Byte Registers (RXH, RXM, RXL)
  • 4.4.5.9 Transmit Byte Registers (TXH, TXM, TXL)
  • 4.4.5.10 Registers After Reset
• Table45 HI Registers after Reset (Host Side) 
  • 4.4.6 HI Signals
    • 4.4.6.1 HI Data Bus (H0–H7)
    • 4.4.6.2 HI Address (HOA2–HOA0)
    • 4.4.6.3 HI Read/Write (HR/W)
    • 4.4.6.4 HI Enable (HEN)
    • 4.4.6.5 Host Request (HOREQ)
    • 4.4.6.6 Host Acknowledge (HACK)
• Table46 Port B Pin Definitions
• Figure414 Host Processor Transfer Timing
  • 4.4.7 Servicing the HI
    • 4.4.7.1 HI—Host Processor Data Transfer
    • 4.4.7.2 Host Interrupts using Host Request (HOREQ)
    • 4.4.7.3 Polling
    • 4.4.7.4 Servicing Non-DMA Interrupts
• Figure415 Interrupt Vector Register Read Timing
• Figure416 HI Interrupt Structure
• Figure417 DMA Transfer Logic and Timing
  • 4.4.7.5 Servicing DMA Interrupts
  • 4.4.8 Host Interface Application Examples
    • 4.4.8.1 HI Initialization
• Figure418 HI Initialization Flowchart
• Figure419 HI Initialization—DSP Side
• Figure420 HI Initialization—Host Side, Interrupt Mode
• Figure421 HI Mode and INIT Bits
  • 4.4.8.2 Polling/Interrupt Controlled Data Transfer
• Figure422 HI Initialization—Host Side, Polling Mode
• Figure423 HI Configuration—Host Side
• Figure424 HI Initialization–Host Side, DMA Mode
• Figure425 Bits Used for Host-to-DSP Transfer
  • 4.4.8.2.1 Host to DSP—Data Transfer
• Figure426 Data Transfer from Host to DSP
  • 4.4.8.2.2 Host to DSP–Command Vector
• Figure427 Host Command
• Figure428 Receive Data from Host—Main Program
• Figure429 Receive Data from Host Interrupt Routine
  • 4.4.8.2.3 Host to DSP—Bootstrap Loading Using the HI
• Figure430 Transmit/Receive Byte Registers
• Figure431 Bootstrap Using the Host Interface
  • 4.4.8.2.4 DSP to Host—Data Transfer
• Figure432 Bits Used for DSP to Host Transfer
• Figure433 Data Transfer from DSP to Host
  • 4.4.8.3 DMA Data Transfer
• Figure434 Main Program: Transmit 24-bit Data to Host
• Figure435 HI Hardware–DMA Mode
• Figure436 DMA Transfer and HI Interrupts
  • 4.4.8.3.1 Host to DSP—Internal Processing
  • 4.4.8.3.2 Host to DSP—DMA Procedure
• Figure437 Host to DSP DMA Procedure
  • 4.4.8.3.3 DSP to HI —Internal Processing
  • 4.4.8.3.4 DSP to Host—DMA Procedure
  • 4.4.8.4 HI Port Usage Considerations—Host Side
    • 4.4.8.4.1 Unsynchronized Reading of Receive Byte Registers
    • 4.4.8.4.2 Overwriting Transmit Byte Registers
    • 4.4.8.4.3 Synchronization of Status Bits from DSP to Host
    • 4.4.8.4.4 Overwriting the Host Vector
    • 4.4.8.4.5 Cancelling a Pending Host Command interrupt
    • 4.4.8.4.6 Coordinating Data Transfers
    • 4.4.8.4.7 Unused Pins
• Serial Host Interface
  • 5.1 Introduction
  • 5.2 Serial Host Interface Internal Architecture
• Figure51 Serial Host Interface Block Diagram
  • 5.3 SHI Clock Generator
• Figure52 SHI Clock Generator
  • 5.4 Serial Host Interface Programming Model
• Figure53 SHI Programming Model—Host Side
• Figure54 SHI Programming Model—DSP Side
• Table51 SHI Interrupt Vectors
• Table52 SHI Internal Interrupt Priorities
  • 5.4.1 SHI Input/Output Shift Register (IOSR)—Host Side
• Figure55 SHI I/O Shift Register (IOSR)
  • 5.4.2 SHI Host Transmit Data Register (HTX)—DSP Side
  • 5.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side
  • 5.4.4 SHI Slave Address Register (HSAR)—DSP Side
    • 5.4.4.1 HSAR Reserved Bits—Bits 17–0,19
    • 5.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18
  • 5.4.5 SHI Clock Control Register (HCKR)—DSP Side
    • 5.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
• Figure56 SPI Data-To-Clock Timing Diagram
  • 5.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2
  • 5.4.5.3 HCKR Divider Modulus Select (HDM[5:0])—Bits 8–3
  • 5.4.5.4 HCKR Reserved Bits—Bits 23–14, 11–9
  • 5.4.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12
• Table53 SHI Noise Reduction Filter Mode
  • 5.4.6 SHI Control/Status Register (HCSR)—DSP Side
    • 5.4.6.1 HCSR Host Enable (HEN)—Bit 0
      • 5.4.6.1.1 SHI Individual Reset
    • 5.4.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1
    • 5.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2
• Table54 SHI Data Size 
  • 5.4.6.4 HCSR Reserved Bits—Bits 23, 18, 16, and 4
  • 5.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5
  • 5.4.6.6 HCSR Master Mode (HMST)—Bit 6
  • 5.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
• Table55 HREQ Function In SHI Slave Modes
  • 5.4.6.8 HCSR Idle (HIDLE)—Bit 9
  • 5.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
  • 5.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
  • 5.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
• Table56 HCSR Receive Interrupt Enable Bits 
  • 5.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
  • 5.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15
  • 5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17
  • 5.4.6.15 Host Receive FIFO Full (HRFF)—Bit 19
  • 5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20
  • 5.4.6.17 Host Bus Error (HBER)—Bit 21
  • 5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22
  • 5.5 Characteristics Of The SPI Bus
  • 5.6 Characteristics Of The I2C Bus
    • 5.6.1 Overview
• Figure57 I2C Bit Transfer
• Figure58 I2C Start and Stop Events
• Figure59 Acknowledgment on the I2C Bus
  • 5.6.2 I2C Data Transfer Formats
• Figure510 I2C Bus Protocol For Host Write Cycle
• Figure511 I2C Bus Protocol For Host Read Cycle
  • 5.7 SHI Programming Considerations
    • 5.7.1 SPI Slave Mode
    • 5.7.2 SPI Master Mode
    • 5.7.3 I2C Slave Mode
      • 5.7.3.1 Receive Data in I2C Slave Mode
      • 5.7.3.2 Transmit Data In I2C Slave Mode
    • 5.7.4 I2C Master Mode
      • 5.7.4.1 Receive Data in I2C Master Mode
      • 5.7.4.2 Transmit Data In I2C Master Mode
    • 5.7.5 SHI Operation During Stop
• Serial Audio Interface
  • 6.1 Introduction
  • 6.2 Serial Audio Interface Internal Architecture
    • 6.2.1 Baud-Rate Generator
• Figure61 SAI Baud-Rate Generator Block Diagram
  • 6.2.2 Receive Section Overview
• Figure62 SAI Receive Section Block Diagram
  • 6.2.3 SAI Transmit Section Overview
• Figure63 SAI Transmit Section Block Diagram
  • 6.3 Serial Audio Interface Programming Model
• Figure64 SAI Registers
• Table61 SAI Interrupt Vector Locations
• Table62 SAI Internal Interrupt Priorities
  • 6.3.1 Baud Rate Control Register (BRC)
    • 6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0
    • 6.3.1.2 Prescaler Range (PSR)—Bit 8
    • 6.3.1.3 BRC Reserved Bits—Bits 15–9
  • 6.3.2 Receiver Control/Status Register (RCS)
    • 6.3.2.1 RCS Receiver 0 Enable (R0EN)—Bit 0
    • 6.3.2.2 RCS Receiver 1 Enable (R1EN)—Bit 1
    • 6.3.2.3 RCS Reserved Bit—Bits 13 and 2
    • 6.3.2.4 RCS Receiver Master (RMST)—Bit 3
    • 6.3.2.5 RCS Receiver Word Length Control (RWL[1:0])—Bits 4 and 5
• Table63 Receiver Word Length Control
  • 6.3.2.6 RCS Receiver Data Shift Direction (RDIR)—Bit 6
• Figure65 Receiver Data Shift Direction (RDIR) Programming
  • 6.3.2.7 RCS Receiver Left Right Selection (RLRS)—Bit 7
• Figure66 Receiver Left/Right Selection (RLRS) Programming
  • 6.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8
• Figure67 Receiver Clock Polarity (RCKP) Programming
  • 6.3.2.9 RCS Receiver Relative Timing (RREL)—Bit 9
• Figure68 Receiver Relative Timing (RREL) Programming
  • 6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 10
• Figure69 Receiver Data Word Truncation (RDWT) Programming
  • 6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11
  • 6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12
  • 6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14
  • 6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15
  • 6.3.3 SAI Receive Data Registers (RX0 and RX1)
  • 6.3.4 Transmitter Control/Status Register (TCS)
    • 6.3.4.1 TCS Transmitter 0 Enable (T0EN)—Bit 0
    • 6.3.4.2 TCS Transmitter 1 Enable (T1EN)—Bit 1
    • 6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2
    • 6.3.4.4 TCS Transmitter Master (TMST)—Bit 3
    • 6.3.4.5 TCS Transmitter Word Length Control (TWL[1:0])—Bits 4 & 5
• Table64 Transmitter Word Length 
  • 6.3.4.6 TCS Transmitter Data Shift Direction (TDIR)—Bit 6
• Figure610 Transmitter Data Shift Direction (TDIR) Programming
  • 6.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7
• Figure611 Transmitter Left/Right Selection (TLRS) Programming
  • 6.3.4.8 TCS Transmitter Clock Polarity (TCKP)—Bit 8
• Figure612 Transmitter Clock Polarity (TCKP) Programming
  • 6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9
• Figure613 Transmitter Relative Timing (TREL) Programming
  • 6.3.4.10 TCS Transmitter Data Word Expansion (TDWE)—Bit 10
• Figure614 Transmitter Data Word Expansion (TDWE) Programming
  • 6.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 11
  • 6.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 12
  • 6.3.4.13 TCS Reserved Bit—Bit 13
  • 6.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 14
  • 6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15
  • 6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0)
  • 6.4 Programming Considerations
    • 6.4.1 SAI Operation During Stop
    • 6.4.2 Initiating a Transmit Session
    • 6.4.3 Using a Single Interrupt to Service Both Receiver and Transmitter Sections
    • 6.4.4 SAI State Machine
• GPIO
  • 7.1 Introduction
  • 7.2 GPIO Programming Model
• Figure71 GPIO Control/Data Register
  • 7.3 GPIO Register (GPIOR)
    • 7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0
    • 7.3.2 GPIOR Data Direction Bits (GDD[7:0])—Bits 15–8
• Table71 GPIO Pin Configuration
  • 7.3.3 GPIOR Control Bits (GC[7:0])—Bits 23–16
• Figure72 GPIO Circuit Diagram
• Digital Audio Transmitter
  • 8.1 Overview
• Figure81 Digital Audio Transmitter (DAX) Block Diagram
  • 8.2 DAX Signals
  • 8.3 DAX Functional Overview
  • 8.4 DAX Programming Model
• Table81 DAX Interrupt Vectors
• Table82 DAX Interrupt Priority
  • 8.5 DAX Internal Architecture
• Figure82 DAX Programming Mode
  • 8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB)
  • 8.5.2 DAX Audio Data Buffer (XADBUF)
  • 8.5.3 DAX Audio Data Shift Register (XADSR)
  • 8.5.4 DAX Control Register (XCTR)
    • 8.5.4.1 DAX Enable (XEN)—Bit 0
    • 8.5.4.2 DAX Interrupt Enable (XIEN)—Bit 1
    • 8.5.4.3 DAX Stop Control (XSTP)—Bit 2
    • 8.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4
• Table83 Clock Source Selection
  • 8.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-23
  • 8.5.4.6 DAX Channel A Validity (XVA)—Bit 10
  • 8.5.4.7 DAX Channel A User Data (XUA)—Bit 11
  • 8.5.4.8 DAX Channel A Channel Status (XCA)—Bit 12
  • 8.5.4.9 DAX Channel B Validity (XVB)—Bit 13
  • 8.5.4.10 DAX Channel B User Data (XUB)—Bit 14
  • 8.5.4.11 DAX Channel B Channel Status (XCB)—Bit 15
  • 8.5.5 DAX Status Register (XSTR)
    • 8.5.5.1 DAX Audio Data Register Empty (XADE)—Bit 0
    • 8.5.5.2 XSTR Reserved Bits—Bits 1, 5–23
    • 8.5.5.3 DAX Transmit Underrun Error Flag (XAUR)—Bit 2
    • 8.5.5.4 DAX Block Transfer Flag (XBLK)—Bit 3
• Figure83 DAX Relative Timing
  • 8.5.5.5 DAX Transmit In Progress (XTIP)—Bit 4
  • 8.5.6 DAX Non-Audio Data Buffer (XNADBUF)
  • 8.5.7 DAX Parity Generator (PRTYG)
  • 8.5.8 DAX Biphase Encoder
  • 8.5.9 DAX Preamble Generator
• Table84 Preamble Bit Patterns 
• Figure84 Preamble sequence
  • 8.5.10 DAX Clock Multiplexer
• Figure85 Clock Multiplexer Diagram
  • 8.5.11 DAX State Machine
  • 8.6 DAX Programming Considerations
    • 8.6.1 Initiating A Transmit Session
    • 8.6.2 Transmit Register Empty Interrupt Handling
    • 8.6.3 Block Transferred Interrupt Handling
    • 8.6.4 DAX Operation During Stop
• Bootstrap ROM Contents
  • A.1 INTRODUCTION
  • A.2 BOOTSTRAPPING THE DSP
  • A.3 Bootstrap Program Listing
• Programming Reference
  • B.1 Introduction
  • B.2 Peripheral Addresses
  • B.3 Interrupt Addresses
  • B.4 Interrupt Priorities
  • B.5 Instruction Set Summary
  • B.6 Programming Sheets
    • FigureB1 On-chip Peripheral Memory Map
  • TableB1 Interrupt Starting Addresses and Sources (Continued)
  • TableB2 Interrupt Priorities Within an IPL (Continued)
  • TableB3 Instruction Set Summary (Sheet 7 of 7)