Document Outline

• Title Page
• Contact Information
• Table of Contents
• List of Figures
• List of Tables
• List of Examples
• About This Book
• Chapter1 Introduction
  • 1.1 Features of the MC68VZ328
  • 1.2 CPU
    • 1.2.1 CPU Programming Model
    • 1.2.2 Data and Address Mode Types
    • 1.2.3 FLX68000 Instruction Set
  • 1.3 Modules of the MC68VZ328
    • 1.3.1 Memory Controller
    • 1.3.2 Clock Generation Module and Power Control Module
    • 1.3.3 System Control
    • 1.3.4 Chip-Select Logic
    • 1.3.5 DRAM Controller
    • 1.3.6 LCD Controller
    • 1.3.7 Interrupt Controller
    • 1.3.8 General-Purpose I/O (GPIO) Lines
    • 1.3.9 Real-Time Clock
    • 1.3.10 General-Purpose Timer
    • 1.3.11 Serial Peripheral Interfaces (SPI)
    • 1.3.12 Universal Asynchronous Receiver/Transmitter (UART) Modules
    • 1.3.13 Pulse-Width Modulators (PWM)
    • 1.3.14 In-Circuit Emulation Module
    • 1.3.15 Bootstrap Mode
• Chapter2 Signal Descriptions
  • 2.1 Signals Grouped by Function
  • 2.2 Power and Ground Signals
  • 2.3 Clock and System Control Signals
  • 2.4 Address Bus Signals
  • 2.5 Data Bus Signals
  • 2.6 Bus Control Signals
  • 2.7 Interrupt Controller Signals
  • 2.8 LCD Controller Signals
  • 2.9 UART 1 and UART 2 Controller Signals
  • 2.10 Timer Signals
  • 2.11 Pulse-Width Modulator Signals
  • 2.12 Serial Peripheral Interface 1 Signals
  • 2.13 Serial Peripheral Interface 2 Signals
  • 2.14 Chip-Select and EDO RAM Interface Signals
  • 2.15 SDRAM Interface Signals
  • 2.16 In-Circuit Emulation (ICE) Signals
• Chapter3 Memory Map
  • 3.1 Programmer’s Memory Map
• Chapter4 Clock Generation Module and Power Control Module
  • 4.1 Introduction to the Clock Generation Module
  • 4.2 CGM Operational Overview
  • 4.3 Detailed CGM Clock Descriptions
    • 4.3.1 CLK32 Clock Signal
    • 4.3.2 PLLCLK Clock Signal
      • 4.3.2.1 PLLCLK Initial Power-up Sequence
      • 4.3.2.2 PLL Frequency Selection
      • 4.3.2.3 PLLCLK Frequency Selection Programming Example
      • 4.3.2.4 Programming Considerations When Changing Frequencies
  • 4.4 CGM Programming Model
    • 4.4.1 PLL Control Register
    • 4.4.2 PLL Frequency Select Register
  • 4.5 Introduction to the Power Control Module
    • 4.5.1 Operating the PCM
      • 4.5.1.1 Normal Mode
      • 4.5.1.2 Burst Mode
      • 4.5.1.3 Doze Mode
      • 4.5.1.4 Sleep Mode
    • 4.5.2 CGM Operation During Sleep Mode
    • 4.5.3 Burst Mode Operation
    • 4.5.4 Power Control Register
• Chapter5 System Control
  • 5.1 System Control Operation
    • 5.1.1 Bus Monitors and Watchdog Timers
  • 5.2 Programming Model
    • 5.2.1 System Control Register
    • 5.2.2 Peripheral Control Register
    • 5.2.3 ID Register
    • 5.2.4 I/O Drive Control Register
• Chapter6 Chip-Select Logic
  • 6.1 Overview of the CSL
  • 6.2 Chip-Select Operation
    • 6.2.1 Memory Protection
    • 6.2.2 Programmable Data Bus Size
    • 6.2.3 Overlapping Chip-Select Registers
  • 6.3 Programming Model
    • 6.3.1 Chip-Select Group Base Address Registers
    • 6.3.2 Chip-Select Upper Group Base Address Register
    • 6.3.3 Chip-Select Registers
    • 6.3.4 Emulation Chip-Select Register
    • 6.3.5 Chip-Select Control Register 1
    • 6.3.6 Chip-Select Control Register 2
    • 6.3.7 Chip-Select Control Register 3
• Chapter7 DRAM Controller
  • 7.1 Introduction to the DRAM Controller
  • 7.2 DRAM Controller Operation
    • 7.2.1 Address Multiplexing
    • 7.2.2 DTACK Generation
    • 7.2.3 Refresh Control
    • 7.2.4 LCD Interface
    • 7.2.5 8-Bit Mode
    • 7.2.6 Low-Power Standby Mode
    • 7.2.7 Data Retention During Reset
    • 7.2.8 Data Retention Sequence
  • 7.3 Programming Model
    • 7.3.1 DRAM Memory Configuration Register
    • 7.3.2 DRAM Control Register
    • 7.3.3 SDRAM Control Register
    • 7.3.4 SDRAM Power-down Register
• Chapter8 LCD Controller
  • 8.1 LCD Controller Features
  • 8.2 LCD Controller Operation
    • 8.2.1 Connecting the LCD Controller to an LCD Panel
      • 8.2.1.1 Panel Interface Timing
    • 8.2.2 Controlling the Display
      • 8.2.2.1 Format of the LCD Screen
      • 8.2.2.2 Format of the Cursor
      • 8.2.2.3 Mapping the Display Data
      • 8.2.2.4 Generating Grayscale Tones
    • 8.2.3 Using Low-Power Mode
    • 8.2.4 Using the DMA Controller
      • 8.2.4.1 Bus Bandwidth Calculation Example
    • 8.2.5 Self-Refresh Mode
      • 8.2.5.1 Entering Self-Refresh Mode
      • 8.2.5.2 Canceling Self-Refresh Mode
  • 8.3 Programming Model
    • 8.3.1 LCD Screen Starting Address Register
    • 8.3.2 LCD Virtual Page Width Register
    • 8.3.3 LCD Screen Width Register
    • 8.3.4 LCD Screen Height Register
    • 8.3.5 LCD Cursor X Position Register
    • 8.3.6 LCD Cursor Y Position Register
    • 8.3.7 LCD Cursor Width and Height Register
    • 8.3.8 LCD Blink Control Register
    • 8.3.9 LCD Panel Interface Configuration Register
    • 8.3.10 LCD Polarity Configuration Register
    • 8.3.11 LACD Rate Control Register
    • 8.3.12 LCD Pixel Clock Divider Register
    • 8.3.13 LCD Clocking Control Register
    • 8.3.14 LCD Refresh Rate Adjustment Register
    • 8.3.15 LCD Panning Offset Register
    • 8.3.16 LCD Frame Rate Control Modulation Register
    • 8.3.17 LCD Gray Palette Mapping Register
    • 8.3.18 PWM Contrast Control Register
    • 8.3.19 Refresh Mode Control Register
    • 8.3.20 DMA Control Register
  • 8.4 Programming Example
• Chapter9 Interrupt Controller
  • 9.1 Interrupt Processing
  • 9.2 Exception Vectors
  • 9.3 Reset
    • 9.3.1 Operation Mode Selection During Reset
    • 9.3.2 Data Bus Width for Boot Device Operation
  • 9.4 Interrupt Controller Operation
    • 9.4.1 Interrupt Priority Processing
    • 9.4.2 Interrupt Vectors
  • 9.5 Vector Generation
  • 9.6 Programming Model
    • 9.6.1 Interrupt Vector Register
    • 9.6.2 Interrupt Control Register
    • 9.6.3 Interrupt Mask Register
    • 9.6.4 Interrupt Status Register
    • 9.6.5 Interrupt Pending Register
    • 9.6.6 Interrupt Level Register
  • 9.7 Keyboard Interrupts
  • 9.8 Pen Interrupts
• Chapter10 I/O Ports
  • 10.1 Port Configuration
  • 10.2 Status of I/O Ports During Reset
    • 10.2.1 Warm Reset
    • 10.2.2 Power-up Reset
    • 10.2.3 Summary of Port Behavior During Reset
  • 10.3 I/O Port Operation
    • 10.3.1 Data Flow from the I/O Module
    • 10.3.2 Data Flow to the I/O Module
    • 10.3.3 Operating a Port as GPIO
    • 10.3.4 Port Pull-up and Pull-down Resistors
  • 10.4 Programming Model
    • 10.4.1 Port A Registers
      • 10.4.1.1 Port A Direction Register
      • 10.4.1.2 Port A Data Register
      • 10.4.1.3 Port A Pull-up Enable Register
    • 10.4.2 Port B Registers
      • 10.4.2.1 Port B Direction Register
      • 10.4.2.2 Port B Data Register
      • 10.4.2.3 Port B Dedicated I/O Functions
      • 10.4.2.4 Port B Pull-up Enable Register
      • 10.4.2.5 Port B Select Register
    • 10.4.3 Port C Registers
      • 10.4.3.1 Port C Direction Register
      • 10.4.3.2 Port C Data Register
      • 10.4.3.3 Port C Dedicated I/O Functions
      • 10.4.3.4 Port C Pull-down Enable Register
      • 10.4.3.5 Port C Select Register
    • 10.4.4 Port D Operation
    • 10.4.5 Port D Registers
      • 10.4.5.1 Port D Direction Register
      • 10.4.5.2 Port D Data Register
      • 10.4.5.3 Port D Interrupt Options
      • 10.4.5.4 Port D Pull-up Enable Register
      • 10.4.5.5 Port D Select Register
      • 10.4.5.6 Port D Polarity Register
      • 10.4.5.7 Port D Interrupt Request Enable Register
      • 10.4.5.8 Port D Keyboard Enable Register
      • 10.4.5.9 Port D Interrupt Request Edge Register
    • 10.4.6 Port E Registers
      • 10.4.6.1 Port E Direction Register
      • 10.4.6.2 Port E Data Register
      • 10.4.6.3 Port E Dedicated I/O Functions
      • 10.4.6.4 Port E Pull-up Enable Register
      • 10.4.6.5 Port E Select Register
    • 10.4.7 Port F Registers
      • 10.4.7.1 Port F Direction Register
      • 10.4.7.2 Port F Data Register
      • 10.4.7.3 Port F Dedicated I/O Functions
      • 10.4.7.4 Port F Pull-up/Pull-down Enable Register
      • 10.4.7.5 Port F Select Register
    • 10.4.8 Port G Registers
      • 10.4.8.1 Port G Direction Register
      • 10.4.8.2 Port G Data Register
      • 10.4.8.3 Port G Dedicated I/O Functions
      • 10.4.8.4 Port G Operational Considerations
      • 10.4.8.5 Port G Pull-up Enable Register
      • 10.4.8.6 Port G Select Register
    • 10.4.9 Port J Registers
      • 10.4.9.1 Port J Direction Register
      • 10.4.9.2 Port J Data Register
      • 10.4.9.3 Port J Dedicated I/O Functions
      • 10.4.9.4 Port J Pull-up Enable Register
      • 10.4.9.5 Port J Select Register
    • 10.4.10 Port K Registers
      • 10.4.10.1 Port K Direction Register
      • 10.4.10.2 Port K Data Register
      • 10.4.10.3 Port K Dedicated I/O Functions
      • 10.4.10.4 Port K Pull-up/Pull-down Enable Register
      • 10.4.10.5 Port K Select Register
    • 10.4.11 Port M Registers
      • 10.4.11.1 Port M Direction Register
      • 10.4.11.2 Port M Data Register
      • 10.4.11.3 Port M Dedicated I/O Functions
      • 10.4.11.4 Port M Pull-up/Pull-down Enable Register
      • 10.4.11.5 Port M Select Register
• Chapter11 Real-Time Clock
  • 11.1 RTC Overview
    • 11.1.1 Prescaler
    • 11.1.2 Time-of-Day Counter
    • 11.1.3 Alarm
    • 11.1.4 Watchdog Timer
    • 11.1.5 Real-Time Interrupt Timer
    • 11.1.6 Minute Stopwatch
      • 11.1.6.1 Minute Stopwatch Application Example
  • 11.2 Programming Model
    • 11.2.1 RTC Time Register
    • 11.2.2 RTC Day Count Register
    • 11.2.3 RTC Alarm Register
    • 11.2.4 RTC Day Alarm Register
    • 11.2.5 Watchdog Timer Register
    • 11.2.6 RTC Control Register
    • 11.2.7 RTC Interrupt Status Register
    • 11.2.8 RTC Interrupt Enable Register
    • 11.2.9 Stopwatch Minutes Register
• Chapter12 General-Purpose Timers
  • 12.1 GP Timer Overview
    • 12.1.1 Clock Source and Prescaler
    • 12.1.2 Timer Events and Modes of Operation
      • 12.1.2.1 Restart Mode
      • 12.1.2.2 Free-Running Mode
    • 12.1.3 Timer Capture Register
    • 12.1.4 TOUT/TIN/PB6 Pin
    • 12.1.5 Cascaded Timers
      • 12.1.5.1 Compare and Capture Using Cascaded Timers
  • 12.2 Programming Model
    • 12.2.1 Timer Control Registers 1 and 2
    • 12.2.2 Timer Prescaler Registers 1 and 2
    • 12.2.3 Timer Compare Registers 1 and 2
    • 12.2.4 Timer Capture Registers 1 and 2
    • 12.2.5 Timer Counter Registers 1 and 2
    • 12.2.6 Timer Status Registers 1 and 2
• Chapter13 Serial Peripheral Interface 1 and 2
  • 13.1 SPI 1 Overview
  • 13.2 SPI 1 Operation
    • 13.2.1 Using SPI 1 as Master
    • 13.2.2 Using SPI 1 as Slave
    • 13.2.3 SPI 1 Phase and Polarity Configurations
    • 13.2.4 SPI 1 Signals
  • 13.3 SPI 1 Programming Model
    • 13.3.1 SPI 1 Receive Data Register
    • 13.3.2 SPI 1 Transmit Data Register
    • 13.3.3 SPI 1 Control/Status Register
    • 13.3.4 SPI 1 Interrupt Control/Status Register
    • 13.3.5 SPI 1 Test Register
    • 13.3.6 SPI 1 Sample Period Control Register
  • 13.4 SPI 2 Overview
  • 13.5 SPI 2 Operation
    • 13.5.1 SPI 2 Phase and Polarity Configurations
    • 13.5.2 SPI 2 Signals
  • 13.6 SPI 2 Programming Model
    • 13.6.1 SPI 2 Data Register
    • 13.6.2 SPI 2 Data Register Timing
    • 13.6.3 SPI 2 Control/Status Register
• Chapter14 Universal Asynchronous Receiver/Transmitter 1 and 2
  • 14.1 Introduction to the UARTs
  • 14.2 Serial Operation
    • 14.2.1 NRZ Mode
    • 14.2.2 IrDA Mode
    • 14.2.3 Serial Interface Signals
  • 14.3 UART Operation
    • 14.3.1 Transmitter Operation
      • 14.3.1.1 TxFIFO Buffer Operation
      • 14.3.1.2 CTS Signal Operation
    • 14.3.2 Receiver Operation
      • 14.3.2.1 Rx FIFO Buffer Operation
    • 14.3.3 Baud Rate Generator Operation
      • 14.3.3.1 Divider
      • 14.3.3.2 Non-Integer Prescaler
      • 14.3.3.3 Integer Prescaler
  • 14.4 Programming Model
    • 14.4.1 UART 1 Status/Control Register
    • 14.4.2 UART 1 Baud Control Register
    • 14.4.3 UART 1 Receiver Register
    • 14.4.4 UART 1 Transmitter Register
    • 14.4.5 UART 1 Miscellaneous Register
    • 14.4.6 UART 1 Non-Integer Prescaler Register
    • 14.4.7 Non-Integer Prescaler Programming Example
    • 14.4.8 UART 2 Status/Control Register
    • 14.4.9 UART 2 Baud Control Register
    • 14.4.10 UART 2 Receiver Register
    • 14.4.11 UART 2 Transmitter Register
    • 14.4.12 UART 2 Miscellaneous Register
    • 14.4.13 UART 2 Non-Integer Prescaler Register
    • 14.4.14 FIFO Level Marker Interrupt Register
• Chapter15 Pulse-Width Modulator 1 and 2
  • 15.1 Introduction to PWM Operation
    • 15.1.1 PWM Clock Signals
  • 15.2 PWM 1
  • 15.3 PWM Operation
    • 15.3.1 Playback Mode
      • 15.3.1.1 Tone Mode
      • 15.3.1.2 D/A Mode
  • 15.4 Programming Model
    • 15.4.1 PWM 1 Control Register
    • 15.4.2 PWM 1 Sample Register
    • 15.4.3 PWM 1 Period Register
    • 15.4.4 PWM 1 Counter Register
  • 15.5 PWM 2
    • 15.5.1 PWM 2 Control Register
    • 15.5.2 PWM 2 Period Register
    • 15.5.3 PWM 2 Pulse Width Register
    • 15.5.4 PWM 2 Counter Register
• Chapter16 In-Circuit Emulation
  • 16.1 ICE Operation
    • 16.1.1 Entering Emulation Mode
    • 16.1.2 Detecting Breakpoints
      • 16.1.2.1 Execution Breakpoints vs. Bus Breakpoints
    • 16.1.3 Using the Signal Decoder
    • 16.1.4 Using the Interrupt Gate Module
    • 16.1.5 Using the A-Line Insertion Unit
  • 16.2 Programming Model
    • 16.2.1 In-Circuit Emulation Module Address Compare and Mask Registers
    • 16.2.2 In-Circuit Emulation Module Control Compare and Mask Register
    • 16.2.3 In-Circuit Emulation Module Control Register
    • 16.2.4 In-Circuit Emulation Module Status Register
  • 16.3 Typical Design Programming Example
    • 16.3.1 Host Interface
    • 16.3.2 Dedicated Debug Monitor Memory
    • 16.3.3 Emulation Memory Mapping FPGA and Emulation Memory
    • 16.3.4 Optional Extra Hardware Breakpoint
    • 16.3.5 Optional Trace Module
  • 16.4 Plug-in Emulator Design Example
  • 16.5 Application Development Design Example
• Chapter17 Bootstrap Mode
  • 17.1 Bootstrap Mode Operation
    • 17.1.1 Entering Bootstrap Mode
    • 17.1.2 Bootstrap Record Format
      • 17.1.2.1 Data B-Record Format
      • 17.1.2.2 Execution B-Record Format
    • 17.1.3 Setting Up the RS-232 Terminal
    • 17.1.4 Changing the Speed of Communication
    • 17.1.5 System Initialization Programming Example
    • 17.1.6 Application Programming Example
    • 17.1.7 Example of Instruction Buffer Usage
  • 17.2 Bootloader Flowchart
  • 17.3 Special Notes
• Chapter18 Application Guide
  • 18.1 Design Checklist
    • 18.1.1 Determining the Chip ID and Version
    • 18.1.2 8-Bit Bus Width Issues
    • 18.1.3 Clock and Layout Considerations
    • 18.1.4 Bus and I/O Considerations
• Chapter19 Electrical Characteristics
  • 19.1 Maximum Ratings
  • 19.2 DC Electrical Characteristics
  • 19.3 AC Electrical Characteristics
    • 19.3.1 CLKO Reference to Chip-Select Signals Timing
    • 19.3.2 Chip-Select Read Cycle Timing
    • 19.3.3 Chip-Select Write Cycle Timing
    • 19.3.4 Chip-Select Flash Write Cycle Timing
    • 19.3.5 Chip-Select Timing Trim
    • 19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)
    • 19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)
    • 19.3.8 DRAM Hidden Refresh Cycle (Normal Mode)
    • 19.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode)
    • 19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)
    • 19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
    • 19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
    • 19.3.13 LCD Controller Timing
    • 19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency=1)
    • 19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency=1)
    • 19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency=1)
    • 19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency=1)
    • 19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency=1)
    • 19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency=1)
    • 19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency=1, Bit APEN of SDRAM Power-down...
    • 19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency=1, Bit RM of DRAM Control Register...
    • 19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register=1)
    • 19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency=1)
    • 19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency=1)
    • 19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency=1)
    • 19.3.26 SPI 1 and SPI 2 Generic Timing
    • 19.3.27 SPI 1 Master Using DATA_READY Edge Trigger
    • 19.3.28 SPI 1 Master Using DATA_READY Level Trigger
    • 19.3.29 SPI 1 Master “Don’t Care” DATA_READY
    • 19.3.30 SPI 1 Slave FIFO Advanced by Bit Count
    • 19.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge
    • 19.3.32 Normal Mode Timing
    • 19.3.33 Emulation Mode Timing
    • 19.3.34 Bootstrap Mode Timing
• Chapter20 Mechanical Data and Ordering Information
  • 20.1 Ordering Information
  • 20.2 TQFP Pin Assignments
  • 20.3 TQFP Package Dimensions
  • 20.4 MAPBGA Pin Assignments
  • 20.5 MAPBGA Package Dimensions
  • 20.6 PCB Finish Requirement
• Index