Document Outline

• Contents
• List of Figures
• List of Tables
• About This Manual
  • Overview of Contents
  • Comments and Suggestions
  • Conventions Used in This Manual
• Programming Issues
  • Introduction
    • The Petra ASIC and Second-Generation MVME1X7 Boards
    • Features
    • Applicable Industry Standards
    • Block Diagram
  • Programming Interfaces
    • MC680X0 MPU
    • Data Bus Structure
    • EEPROMs on the MVME1X7P
      • MVME167
      • MVME177
    • Flash Memory on the MVME177
    • SRAM
    • Onboard SDRAM
    • Battery-Backed-Up RAM and Clock
    • VMEbus Interface
    • I/O Interfaces
      • Serial Port Interface
      • Parallel (Printer) Interface
      • Ethernet Interface
      • SCSI Interface
    • Local Resources
      • Programmable Tick Timers
      • Watchdog Timer
      • Software-Programmable Hardware Interrupts
      • Local Bus Timeout
  • Functional Description
    • VMEbus Interface and VMEchip2
      • VMEchip2 General-Purpose I/O
      • Petra/VMEchip2 Redundant Logic
  • Memory Maps
    • Local Bus Memory Map
      • Normal Address Range
      • Detailed I/O Memory Maps
      • BBRAM/TOD Clock Memory Map
      • Interrupt Acknowledge Map
    • VMEbus Memory Map
      • VMEbus Accesses to the Local Bus
      • VMEbus Short I/O Memory Map
  • Interrupt Handling
    • Example: VMEchip2 Tick Timer 1 Periodic Interrupt
  • Cache Coherency (MVME167P)
  • Cache Coherency (MVME177P)
  • Using Bus Timers
  • Indivisible Cycles
  • Supervisor Stack Pointer (MC68060)
  • Sources of Local Bus Errors
    • Local Bus Timeout
    • VMEbus Access Timeout
    • VMEbus BERR*
    • VMEchip2
    • Bus Error Processing
  • Error Conditions
    • MPU Parity Error
    • MPU Offboard Error
    • MPU TEA - Cause Unidentified
    • MPU Local Bus Time-out
    • DMAC VMEbus Error
    • DMAC Parity Error
    • DMAC Offboard Error
    • DMAC LTO Error
    • DMAC TEA - Cause Unidentified
    • SCC Retry Error
    • SCC Parity Error
    • SCC Offboard Error
    • SCC LTO Error
    • LAN Parity Error
    • LAN Offboard Error
    • LAN LTO Error
    • SCSI Parity Error
    • SCSI Offboard Error
    • SCSI LTO Error
• VMEchip2
  • Introduction
  • Functional Blocks
    • Local-Bus-to-VMEbus Interface
      • Local-Bus-to-VMEbus Requester
    • VMEbus-to-Local-Bus Interface
    • Local-Bus-to-VMEbus DMA Controller
      • No-Address-Increment DMA Transfers
      • DMAC VMEbus Requester
    • Tick and Watchdog Timers
      • Prescaler
      • Tick Timers
      • Watchdog Timer
    • VMEbus Interrupter
    • VMEbus System Controller
      • Arbiter
      • IACK Daisy-Chain Driver
      • Bus Timer
      • Reset Driver
    • Local Bus Interrupter and Interrupt Handler
    • Global Control and Status Registers
  • LCSR Programming Model
    • Programming the VMEbus Slave Map Decoders
      • VMEbus Slave Ending Address Register 1
      • VMEbus Slave Starting Address Register 1
      • VMEbus Slave Ending Address Register 2
      • VMEbus Slave Starting Address Register 2
      • VMEbus Slave Address Translation Address Offset Register 1
      • VMEbus Slave Address Translation Select Register 1
      • VMEbus Slave Address Translation Address Offset Register 2
      • VMEbus Slave Address Translation Select Register 2
      • VMEbus Slave Write Post and Snoop Control Register 2
      • VMEbus Slave Address Modifier Select Register 2
      • VMEbus Slave Write Post and Snoop Control Register 1
      • VMEbus Slave Address Modifier Select Register 1
    • Programming the Local-Bus-to-VMEbus Map Decoders
      • Local Bus Slave (VMEbus Master) Ending Address Register 1
      • Local Bus Slave (VMEbus Master) Starting Address Register 1
      • Local Bus Slave (VMEbus Master) Ending Address Register 2
      • Local Bus Slave (VMEbus Master) Starting Address Register 2
      • Local Bus Slave (VMEbus Master) Ending Address Register 3
      • Local Bus Slave (VMEbus Master) Starting Address Register 3
      • Local Bus Slave (VMEbus Master) Ending Address Register 4
      • Local Bus Slave (VMEbus Master) Starting Address Register 4
      • Local Bus Slave (VMEbus Master) Address Translation Address Register 4
      • Local Bus Slave (VMEbus Master) Address Translation Select Register 4
      • Local Bus Slave (VMEbus Master) Attribute Register 4
      • Local Bus Slave (VMEbus Master) Attribute Register 3
      • Local Bus Slave (VMEbus Master) Attribute Register 2
      • Local Bus Slave (VMEbus Master) Attribute Register 1
      • VMEbus Slave GCSR Group Address Register
      • VMEbus Slave GCSR Board Address Register
      • Local-Bus-to-VMEbus Enable Control Register
      • Local-Bus-to-VMEbus I/O Control Register
      • ROM Control Register
    • Programming the VMEchip2 DMA Controller
    • DMAC Registers
      • EPROM Decoder, SRAM and DMA Control Register
      • Local-Bus-to-VMEbus Requester Control Register
      • DMAC Control Register 1 (bits 07)
      • DMAC Control Register 2 (bits 815)
      • DMAC Control Register 2 (bits 07)
      • DMAC Local Bus Address Counter
      • DMAC VMEbus Address Counter
      • DMAC Byte Counter
      • Table Address Counter
      • VMEbus Interrupter Control Register
      • VMEbus Interrupter Vector Register
      • MPU Status and DMA Interrupt Count Register
      • DMAC Status Register
    • Programming the Tick and Watchdog Timers
      • VMEbus Arbiter Time-Out Control Register
      • DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register
      • VME Access, Local Bus, and Watchdog Time-out Control Register
      • Prescaler Control Register
      • Tick Timer 1 Compare Register
      • Tick Timer 1 Counter
      • Tick Timer 2 Compare Register
      • Tick Timer 2 Counter
      • Board Control Register
      • Watchdog Timer Control Register
      • Tick Timer 2 Control Register
      • Tick Timer 1 Control Register
      • Prescaler Counter
    • Programming the Local Bus Interrupter
      • Local Bus Interrupter Status Register (bits 2431)
      • Local Bus Interrupter Status Register (bits 1623)
      • Local Bus Interrupter Status Register (bits 815)
      • Local Bus Interrupter Status Register (bits 07)
      • Local Bus Interrupter Enable Register (bits 2431)
      • Local Bus Interrupter Enable Register (bits 1623)
      • Local Bus Interrupter Enable Register (bits 815)
      • Local Bus Interrupter Enable Register (bits 07)
      • Software Interrupt Set Register (bits 815)
      • Interrupt Clear Register (bits 2431)
      • Interrupt Clear Register (bits 1623)
      • Interrupt Clear Register (bits 815)
      • Interrupt Level Register 1 (bits 2431)
      • Interrupt Level Register 1 (bits 1623)
      • Interrupt Level Register 1 (bits 815)
      • Interrupt Level Register 1 (bits 07)
      • Interrupt Level Register 2 (bits 2431)
      • Interrupt Level Register 2 (bits 1623)
      • Interrupt Level Register 2 (bits 815)
      • Interrupt Level Register 2 (bits 07)
      • Interrupt Level Register 3 (bits 2431)
      • Interrupt Level Register 3 (bits 1623)
      • Interrupt Level Register 3 (bits 815)
      • Interrupt Level Register 3 (bits 07)
      • Interrupt Level Register 4 (bits 2431)
      • Interrupt Level Register 4 (bits 1623)
      • Interrupt Level Register 4 (bits 815)
      • Interrupt Level Register 4 (bits 07)
      • Vector Base Register
      • I/O Control Register 1
      • I/O Control Register 2
      • I/O Control Register 3
      • Miscellaneous Control Register
  • GCSR Programming Model
    • Programming the GCSR
      • VMEchip2 Revision Register
      • VMEchip2 ID Register
      • VMEchip2 LM/SIG Register
      • VMEchip2 Board Status/Control Register
      • General Purpose Register 0
      • General Purpose Register 1
      • General Purpose Register 2
      • General Purpose Register 3
      • General Purpose Register 4
      • General Purpose Register 5
• PCCchip2
  • Introduction
    • Summary of Major Features
  • Functional Description
    • General Description
    • BBRAM Interface
    • 82596CA LAN Controller Interface
      • MPU Port and MPU Channel Attention
      • MC68040-Bus Master Support for 82596CA
      • LANC Bus Error
      • LANC Interrupt
    • 53C710 SCSI Controller Interface
    • Parallel Port Interface
    • General Purpose I/O Pin
    • CD2401 SCC Interface
    • Tick Timer
  • Overall Memory Map
  • Programming Model
    • Chip ID Register
    • Chip Revision Register
    • General Control Register
    • Vector Base Register
    • Programming the Tick Timers
      • Tick Timer 1 Compare Register
      • Tick Timer 1 Counter
      • Tick Timer 2 Compare Register
      • Tick Timer 2 Counter
      • Prescaler Count Register
      • Prescaler Clock Adjust Register
      • Tick Timer 2 Control Register
      • Tick Timer 1 Control Register
      • General Purpose Input Interrupt Control Register
      • General Purpose Input/Output Pin Control Register
      • Tick Timer 2 Interrupt Control Register
      • Tick Timer 1 Interrupt Control Register
    • SCC Error Status and Interrupt Control Registers
      • SCC Error Status Register
      • SCC Modem Interrupt Control Register
      • SCC Transmit Interrupt Control Register
      • SCC Receive Interrupt Control Register
      • Modem PIACK Register
      • Transmit PIACK Register
      • Receive PIACK Register
    • LANC Error Status and Interrupt Control Registers
      • LANC Error Status Register
      • 82596CA LANC Interrupt Control Register
      • LANC Bus Error Interrupt Control Register
    • Programming the SCSI Error Status and Interrupt Registers
      • SCSI Error Status Register
      • SCSI Interrupt Control Register
    • Programming the Printer Port
      • Printer ACK Interrupt Control Register
      • Printer FAULT Interrupt Control Register
      • Printer SEL Interrupt Control Register
      • Printer PE Interrupt Control Register
      • Printer BUSY Interrupt Control Register
      • Printer Input Status Register
      • Printer Port Control Register
      • Chip Speed Register
      • Printer Data Register
      • Interrupt Priority Level Register
      • Interrupt Mask Level Register
• MCECC Functions
  • Introduction
  • Features
  • Functional Description
    • General Description
    • Performance
    • Cache Coherency
    • ECC
      • Cycle Types
      • Error Reporting
      • Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
      • Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
      • Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
      • Cycle Type = Burst Write
      • Single Bit Error (Cycle Type = Non-Burst Write)
      • Double Bit Error (Cycle Type = Non-Burst Write)
      • Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
      • Single Bit Error (Cycle Type = Scrub)
      • Double Bit Error (Cycle Type = Scrub)
      • Triple (or Greater) Bit Error (Cycle Type = Scrub)
    • Error Logging
    • Scrub
    • Refresh
    • Arbitration
    • Chip Defaults
  • Programming Model
    • Chip ID Register
    • Chip Revision Register
    • Memory Configuration Register
    • Base Address Register
    • DRAM Control Register
    • BCLK Frequency Register
    • Data Control Register
    • Scrub Control Register
    • Scrub Period Register Bits 15-8
    • Scrub Period Register Bits 7-0
    • Chip Prescaler Counter
    • Scrub Time On/Time Off Register
    • Scrub Prescaler Counter (Bits 21-16)
    • Scrub Prescaler Counter (Bits 15-8)
    • Scrub Prescaler Counter (Bits 7-0)
    • Scrub Timer Counter (Bits 15-8)
    • Scrub Timer Counter (Bits 7-0)
    • Scrub Address Counter (Bits 26-24)
    • Scrub Address Counter (Bits 23-16)
    • Scrub Address Counter (Bits 15-8)
    • Scrub Address Counter (Bits 7-4)
    • Error Logger Register
    • Error Address (Bits 31-24)
    • Error Address (Bits 23-16)
    • Error Address (Bits 15-8)
    • Error Address (Bits 7-4)
    • Error Syndrome Register
    • Defaults Register 1
    • Defaults Register 2
    • SDRAM Configuration Register
    • Initialization
  • Syndrome Decoding
• Summary of Changes
  • Introduction
• Printer and Serial Port Connections
  • Introduction
  • Connection Diagrams
• Related Documentation
  • MCG Documents
  • Manufacturers’ Documents
  • Related Specifications
• Index