Document Outline

• DOCUMENT INFORMATION
  • Cover
  • NEC Statement
  • Major Revisions in This Version
  • PREFACE
  • CONTENTS
  • CONTENTS OF FIGURES
  • CONTENTS OF TABLES
• CH 1. GENERAL
  • OUTLINE OF FUNCTIONS
  • ORDERING INFORMATION AND QUALITY GRADE
  • DIFFERENCES BETWEEN uPD75402A AND uPD75402, 75P402
  • BLOCK DIAGRAM
  • PIN CONFIGURATION
    • 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil)
    • 44-Pin Plastic QFP (10mm)
• CH 2. PIN FUNCTIONS
  • uPD75402A PIN FUNCTION LIST
    • Port Pin List
    • List of Pins Other Than Port Pins
  • NORMAL OPERATING MODE
    • P00 to P03 (Port 0), P10, P12 (Port 1)
    • P20 to P23 (Port 2), P30 to P33 (Port 3), P50 to P53 (Port 5), P60 to P63 (Port 6)
    • SCK, SO/SB0, SI
    • INT0
    • INT2
    • PCL
    • X1, X2
    • RESET (Reset)
    • VDD
    • VSS
  • PROM MODE
    • A0 to A14 (Address)
    • O0 to O7 (Data)
    • CE (Chip Enable)
    • MenuMenuMenuMenuOE (Output Enable)
    • VPP
    • VDD
    • VSS
  • PIN INPUT/OUTPUT CIRCUITS
  • UNUSED PIN TREATMENT
  • NOTES ON USE OF P00 PIN AND RESET PIN
• CH 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
  • DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
    • Data Memory Bank Configuration
    • Data Memory Addressing Modes
  • MEMORY-MAPPED I/O
• CH 4. INTERNAL CPU FUNCTIONS
  • PROGRAM COUNTER (PC)
  • PROGRAM MEMORY (ROM)
  • DATA MEMORY (RAM)
  • GENERAL REGISTER
  • ACCUMULATOR
  • STACK POINTER (SP)
  • PROGRAM STATUS WORD (PSW)
• CH 5. PERIPHERAL HARDWARE FUNCTIONS
  • DIGITAL INPUT/OUTPUT PORTS
    • Digital Input/Output Port Types, Characteristics and Configuration
    • Input/Output Mode Setting
    • Digital Input/Output Port Handling Instructions
    • Digital Input/Output Port Operations
    • Internal Pull-up Resistors
    • Digital Input/Output Port Input/Output Timing
  • CLOCK GENERATION CIRCUIT
    • Clock Generation Circuit Configuration
    • Clock Generation Circuit Function and Operaion
    • CPU Clock Setting
    • Differences Between uPD75402A and uPD75402
  • CLOCK OUTPUT CIRCUIT
    • Clock Output Circuit Configuration
    • Clock Output Mode Register (CLOM)
    • Clock Output Procedure
    • Examle of Remote Control Application
  • BASIC INTERVAL TIMER
    • Basic Interval Timer Configuration
    • Basic Intercal Timer Mode Register (BTM)
    • Basic Interval Timer Operation
    • Examples of Basic Interval Timer Applications
  • SERIAL INTERFACE
    • Serial Interface Functions
    • Serial Interface Configuration
    • Register Functions
    • Operation-Halted Mode
    • 3-Wire Serial I/O Mode Operation
    • SBI Mode Operation
• CH 6. INTERRUPT FUNCTIONS
  • INTERRUPT CONTROL CIRCUIT CONFIGURATION
  • INTERRUPT SOURCE TYPES AND VECTOR TABLE
  • INTERRUPT CONTROL CIRCUIT HARDWARE
  • INTERRUPT SEQUENCE
  • MACHINE CYCLES BEFORE INTERRUPT SERVICING
  • INTERRUPT APPLICATIONS
• CH 7. STANDBY FUNCTION
  • STANDBY MODE SETTING AND OPERATION STATES
  • STANDBY MODE RESET
  • OPERATION AFTER STANDBY MODE RESET
  • STANDBY MODE APPLICATION
• CH 8. RESET FUNCTION
• CH 9. INSTRUCTION SET
  • SPECIAL INSTRUCTIONS
    • Bit Manipulation Instructions
    • Stack Instructions
    • Base Correction Instructions
    • Skip Instruction and Number of Machine Cycles Required by Skip
  • INSTRUCTION SET AND ITS OPERATION
  • OPERATION CODE OF EACH INSTRUCTION
  • INSTRUCTION FUNCTIONS AND APPLICATION
    • Move Instructions
    • Table Reference Instructions
    • Arithmetic and Logic Instructions
    • Accumulator Operation Instructions
    • Increment/Decrement Instructions
    • Compare Instructions
    • Carry Flag Operation Instructions
    • Bit Manipuration Instructions
    • Branch Instructions
    • Subroutine Stack Control Instructions
    • Interrupt Control Instructions
    • Input/Output Instructions
    • CPU Control Instructions
• APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLY
• APPENDIX B. DEVELOPMENT TOOLS
• APPENDIX C. MASK ROM ORDERING PROCEDURE
• APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER)
• APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER)