Document Outline

• COVER
• Major Revisions in This Edition
• INTRODUCTION
• CHAPTER 1 GENERAL
  • 1.1 Functional Outline
  • 1.2 Ordering Information
  • 1.3 Differences Between Series Products
  • 1.4 Block Diagram
  • 1.5 Pin Configuration (Top View)
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 Pin Functions of uPD754244
  • 2.2 Description of Pin Functions
    • 2.2.1 P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8)
    • 2.2.2 P70 to P73 (Port 7)
    • 2.2.3 PTO0 to PTO2
    • 2.2.4 INT0
    • 2.2.5 KR4 to KR7
    • 2.2.6 KRREN
    • 2.2.7 TH00 and TH01
    • 2.2.8 AVREF
    • 2.2.9 CL1 and CL2 (uPD754144 only)
    • 2.2.10 X1 and X2 (uPD754244 only)
    • 2.2.11 RESET#
    • 2.2.12 IC
    • 2.2.13 VDD
    • 2.2.14 VSS
  • 2.3 Pin I/O Circuits
  • 2.4 Processing of Unused Pins
• CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP
  • 3.1 Bank Configuration of Data Memory and Addressing Modes
    • 3.1.1 Bank configuration of data memory
    • 3.1.2 Addressing mode of data memory
  • 3.2 Bank Configuration of General-Purpose Registers
  • 3.3 Memory-Mapped I/O
• CHAPTER 4 INTERNAL CPU FUNCTION
  • 4.1 Function to Select MkI and MkII Modes
    • 4.1.1 Difference between MkI and MkII modes
    • 4.1.2 Setting stack bank select register (SBS)
  • 4.2 Program Counter (PC)
  • 4.3 Program Memory (ROM)
  • 4.4 Data Memory (RAM)
    • 4.4.1 Configuration of data memory
    • 4.4.2 Specifying bank of data memory
  • 4.5 General-Purpose Registers
  • 4.6 Accumulator
  • 4.7 Stack Pointer (SP) and Stack Bank Select Register (SBS)
  • 4.8 Program Status Word (PSW)
  • 4.9 Bank Select Register (BS)
• CHAPTER 5 EEPROM
  • 5.1 EEPROM Configuration
  • 5.2 EEPROM Features
  • 5.3 EEPROM Write Control Register (EWC)
  • 5.4 Interrupt Related to EEPROM Control
  • 5.5 EEPROM Manipulation Method
    • 5.5.1 EEPROM manipulation instructions
    • 5.5.2 Read manipulation
    • 5.5.3 Write manipulation
  • 5.6 Cautions on EEPROM Writing
• CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
  • 6.1 Digital I/O Ports
    • 6.1.1 Types, features, and configurations of digital I/O ports
    • 6.1.2 Setting I/O mode
    • 6.1.3 Digital I/O port manipulation instruction
    • 6.1.4 Operation of digital I/O port
    • 6.1.5 Connecting pull-up resistor
    • 6.1.6 I/O timing of digital I/O port
  • 6.2 Clock Generator
    • 6.2.1 Configuration of clock generator
    • 6.2.2 Function and operation of clock generator
    • 6.2.3 Setting CPU clock
  • 6.3 Basic Interval Timer/Watchdog Timer
    • 6.3.1 Configuration of basic interval timer/watchdog timer
    • 6.3.2 Basic interval timer mode register (BTM)
    • 6.3.3 Watchdog timer enable flag (WDTM)
    • 6.3.4 Operation as basic interval timer
    • 6.3.5 Operation as watchdog timer
    • 6.3.6 Other functions
  • 6.4 Timer Counter
    • 6.4.1 Configuration of timer counter
    • 6.4.2 Operation in 8-bit timer counter mode
    • 6.4.3 Operation in PWM pulse generator mode (PWM mode)
    • 6.4.4 Operation in 16-bit timer counter mode
    • 6.4.5 Operation in carrier generator mode (CG mode)
    • 6.4.6 Notes on using timer counter
  • 6.5 Programmable Threshold Port (Analog Input Port)
    • 6.5.1 Configuration and operation of programmable threshold port
    • 6.5.2 Programmable threshold port mode (PTHM) register
    • 6.5.3 Programmable threshold port application
  • 6.6 Bit Sequential Buffer
• CHAPTER 7 INTERRUPT AND TEST FUNCTIONS
  • 7.1 Configuration of Interrupt Controller
  • 7.2 Types of Interrupt Sources and Vector Table
  • 7.3 Hardware Controlling Interrupt Function
  • 7.4 Interrupt Sequence
  • 7.5 Nesting Control of Interrupts
  • 7.6 Servicing of Interrupts Sharing Vector Address
  • 7.7 Machine Cycles Until Interrupt Servicing
  • 7.8 Effective Usage of Interrupts
  • 7.9 Application of Interrupt
  • 7.10 Test Function
    • 7.10.1 Types of test sources
    • 7.10.2 Hardware controlling test function
• CHAPTER 8 STANDBY FUNCTION
  • 8.1 Settings and Operating Statuses of Standby Mode
  • 8.2 Releasing Standby Mode
  • 8.3 Operation After Release of Standby Mode
  • 8.4 Application of Standby Mode
• CHAPTER 9 RESET FUNCTION
  • 9.1 Configuration and Operation of Reset Function
  • 9.2 Watchdog Flag (WDF), Key Return Flag (KRF)
• CHAPTER 10 MASK OPTIONS
  • 10.1 Pin Mask Options
    • 10.1.1 Mask option of P70/KR4 to P73/KR7
    • 10.1.2 RESET# pin mask option
  • 10.2 Oscillation Stabilization Wait Time Mask Option
• CHAPTER 11 INSTRUCTION SET
  • 11.1 Unique Instructions
    • 11.1.1 GETI instruction
    • 11.1.2 Bit manipulation instruction
    • 11.1.3 String-effect instruction
    • 11.1.4 Base number adjustment instruction
    • 11.1.5 Skip instruction and number of machine cycles required for skipping
  • 11.2 Instruction Set and Operation
  • 11.3 Opcode of Each Instruction
  • 11.4 Instruction Function and Application
    • 11.4.1 Transfer instructions
    • 11.4.2 Table reference instructions
    • 11.4.3 Bit transfer instructions
    • 11.4.4 Operation instructions
    • 11.4.5 Accumulator manipulation instructions
    • 11.4.6 Increment/decrement instructions
    • 11.4.7 Compare instructions
    • 11.4.8 Carry flag manipulation instructions
    • 11.4.9 Memory bit manipulation instructions
    • 11.4.10 Branch instructions
    • 11.4.11 Subroutine/stack control instructions
    • 11.4.12 Interrupt control instructions
    • 11.4.13 Input/output instructions
    • 11.4.14 CPU control instruction
    • 11.4.15 Special instructions
• APPENDIX A DEVELOPMENT TOOLS
• APPENDIX B ORDERING MASK ROM
• APPENDIX C INSTRUCTION INDEX
  • C.1 Instruction Index (By Function)
  • C.2 Instruction Index (Alphabetical Order)
• APPENDIX D HARDWARE INDEX
• APPENDIX E REVISION HISTORY