Document Outline

• COVER
• Major Revisions in This Edition
• PREFACE
• CHAPTER 1 GENERAL (uPD78054 Subseries)
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Quality Grade
  • 1.5 Pin Configuration (Top View)
  • 1.6 78K/0 Series Expansion
  • 1.7 Block Diagram
  • 1.8 Outline of Function
  • 1.9 Differences between Standard Quality Grade Products and (A) Products
  • 1.10 Mask Options
• CHAPTER 2 GENERAL (uPD78054Y Subseries)
  • 2.1 Features
  • 2.2 Applications
  • 2.3 Ordering Information
  • 2.4 Quality Grade
  • 2.5 Pin Configuration (Top View)
  • 2.6 78K/0 Series Expansion
  • 2.7 Block Diagram
  • 2.8 Outline of Function
  • 2.9 Mask Options
• CHAPTER 3 PIN FUNCTION (uPD78054 Subseries)
  • 3.1 Pin Function List
    • 3.1.1 Normal operating mode pins
    • 3.1.2 PROM programming mode pins (PROM versions only)
  • 3.2 Description of Pin Functions
    • 3.2.1 P00 to P07 (Port 0)
    • 3.2.2 P10 to P17 (Port 1)
    • 3.2.3 P20 to P27 (Port 2)
    • 3.2.4 P30 to P37 (Port 3)
    • 3.2.5 P40 to P47 (Port 4)
    • 3.2.6 P50 to P57 (Port 5)
    • 3.2.7 P60 to P67 (Port 6)
    • 3.2.8 P70 to P72 (Port 7)
    • 3.2.9 P120 to P127 (Port 12)
    • 3.2.10 P130 and P131 (Port 13)
    • 3.2.11 AVREF0
    • 3.2.12 AVREF1
    • 3.2.13 AVDD
    • 3.2.14 AVSS
    • 3.2.15 RESET#
    • 3.2.16 X1 and X2
    • 3.2.17 XT1 and XT2
    • 3.2.18 VDD
    • 3.2.19 VSS
    • 3.2.20 VPP (PROM versions only)
    • 3.2.21 IC (Mask ROM version only)
  • 3.3 Input/output Circuits and Recommended Connection of Unused Pins
• CHAPTER 4 PIN FUNCTION (uPD78054Y Subseries)
  • 4.1 Pin Function List
    • 4.1.1 Normal operating mode pins
    • 4.1.2 PROM programming mode pins (PROM versions only)
  • 4.2 Description of Pin Functions
    • 4.2.1 P00 to P07 (Port 0)
    • 4.2.2 P10 to P17 (Port 1)
    • 4.2.3 P20 to P27 (Port 2)
    • 4.2.4 P30 to P37 (Port 3)
    • 4.2.5 P40 to P47 (Port 4)
    • 4.2.6 P50 to P57 (Port 5)
    • 4.2.7 P60 to P67 (Port 6)
    • 4.2.8 P70 to P72 (Port 7)
    • 4.2.9 P120 to P127 (Port 12)
    • 4.2.10 P130 and P131 (Port 13)
    • 4.2.11 AVREF0
    • 4.2.12 AVREF1
    • 4.2.13 AVDD
    • 4.2.14 AVSS
    • 4.2.15 RESET#
    • 4.2.16 X1 and X2
    • 4.2.17 XT1 and XT2
    • 4.2.18 VDD
    • 4.2.19 VSS
    • 4.2.20 VPP (PROM versions only)
    • 4.2.21 IC (Mask ROM version only)
  • 4.3 Input/output Circuits and Recommended Connection of Unused Pins
• CHAPTER 5 CPU ARCHITECTURE
  • 5.1 Memory Spaces
    • 5.1.1 Internal program memory space
    • 5.1.2 Internal data memory space
    • 5.1.3 Special Function Register (SFR) area
    • 5.1.4 External memory space
    • 5.1.5 Data memory addressing
  • 5.2 Processor Registers
    • 5.2.1 Control registers
    • 5.2.2 General registers
    • 5.2.3 Special Function Register (SFR)
  • 5.3 Instruction Address Addressing
    • 5.3.1 Relative addressing
    • 5.3.2 Immediate addressing
    • 5.3.3 Table indirect addressing
    • 5.3.4 Register addressing
  • 5.4 Operand Address Addressing
    • 5.4.1 Implied addressing
    • 5.4.2 Register addressing
    • 5.4.3 Direct addressing
    • 5.4.4 Short direct addressing
    • 5.4.5 Special-Function Register (SFR) addressing
    • 5.4.6 Register indirect addressing
    • 5.4.7 Based addressing
    • 5.4.8 Based indexed addressing
    • 5.4.9 Stack addressing
• CHAPTER 6 PORT FUNCTIONS
  • 6.1 Port Functions
  • 6.2 Port Configuration
    • 6.2.1 Port 0
    • 6.2.2 Port 1
    • 6.2.3 Port 2 (uPD78054 Subseries)
    • 6.2.4 Port 2 (uPD78054Y Subseries)
    • 6.2.5 Port 3
    • 6.2.6 Port 4
    • 6.2.7 Port 5
    • 6.2.8 Port 6
    • 6.2.9 Port 7
    • 6.2.10 Port 12
    • 6.2.11 Port 13
  • 6.3 Port Function Control Registers
  • 6.4 Port Function Operations
    • 6.4.1 Writing to input/output port
    • 6.4.2 Reading from input/output port
    • 6.4.3 Operations on input/output port
  • 6.5 Selection of Mask Option
• CHAPTER 7 CLOCK GENERATOR
  • 7.1 Clock Generator Functions
  • 7.2 Clock Generator Configuration
  • 7.3 Clock Generator Control Register
  • 7.4 System Clock Oscillator
    • 7.4.1 Main system clock oscillator
    • 7.4.2 Subsystem clock oscillator
    • 7.4.3 Scaler
    • 7.4.4 When no subsystem clocks are used
  • 7.5 Clock Generator Operations
    • 7.5.1 Main system clock operations
    • 7.5.2 Subsystem clock operations
  • 7.6 Changing System Clock and CPU Clock Settings
    • 7.6.1 Time required for switchover between system clock and CPU clock
    • 7.6.2 System clock and CPU clock switching procedure
• CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  • 8.1 Outline of Timers Incorporated in the uPD78054, 78054Y Subseries
  • 8.2 16-Bit Timer/Event Counter Functions
  • 8.3 16-Bit Timer/Event Counter Configuration
  • 8.4 16-Bit Timer/Event Counter Control Registers
  • 8.5 16-Bit Timer/Event Counter Operations
    • 8.5.1 Interval timer operations
    • 8.5.2 PWM output operations
    • 8.5.3 PPG output operations
    • 8.5.4 Pulse width measurement operations
    • 8.5.5 External event counter operation
    • 8.5.6 Square-wave output operation
    • 8.5.7 One-shot pulse output operation
  • 8.6 16-Bit Timer/Event Counter Operating Precautions
• CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2
  • 9.1 8-Bit Timer/Event Counters 1 and 2 Functions
    • 9.1.1 8-bit timer/event counter mode
    • 9.1.2 16-bit timer/event counter mode
  • 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations
  • 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers
  • 9.4 8-Bit Timer/Event Counters 1 and 2 Operations
    • 9.4.1 8-bit timer/event counter mode
    • 9.4.2 16-bit timer/event counter mode
  • 9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2
• CHAPTER 10 WATCH TIMER
  • 10.1 Watch Timer Functions
  • 10.2 Watch Timer Configuration
  • 10.3 Watch Timer Control Registers
  • 10.4 Watch Timer Operations
    • 10.4.1 Watch timer operation
    • 10.4.2 Interval timer operation
• CHAPTER 11 WATCHDOG TIMER
  • 11.1 Watchdog Timer Functions
  • 11.2 Watchdog Timer Configuration
  • 11.3 Watchdog Timer Control Registers
  • 11.4 Watchdog Timer Operations
    • 11.4.1 Watchdog timer operation
    • 11.4.2 Interval timer operation
• CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
  • 12.1 Clock Output Control Circuit Functions
  • 12.2 Clock Output Control Circuit Configuration
  • 12.3 Clock Output Function Control Registers
• CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
  • 13.1 Buzzer Output Control Circuit Functions
  • 13.2 Buzzer Output Control Circuit Configuration
  • 13.3 Buzzer Output Function Control Registers
• CHAPTER 14 A/D CONVERTER
  • 14.1 A/D Converter Functions
  • 14.2 A/D Converter Configuration
  • 14.3 A/D Converter Control Registers
  • 14.4 A/D Converter Operations
    • 14.4.1 Basic operations of A/D converter
    • 14.4.2 Input voltage and conversion results
    • 14.4.3 A/D converter operating mode
  • 14.5 A/D Converter Cautions
• CHAPTER 15 D/A CONVERTER
  • 15.1 D/A Converter Functions
  • 15.2 D/A Converter Configuration
  • 15.3 D/A Converter Control Registers
  • 15.4 Operations of D/A Converter
  • 15.5 Cautions Related to D/A Converter
• CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (uPD78054 Subseries)
  • 16.1 Serial Interface Channel 0 Functions
  • 16.2 Serial Interface Channel 0 Configuration
  • 16.3 Serial Interface Channel 0 Control Registers
  • 16.4 Serial Interface Channel 0 Operations
    • 16.4.1 Operation stop mode
    • 16.4.2 3-wire serial I/O mode operation
    • 16.4.3 SBI mode operation
    • 16.4.4 2-wire serial I/O mode operation
    • 16.4.5 SCK0#/P27 pin output manipulation
• CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (uPD78054Y Subseries)
  • 17.1 Serial Interface Channel 0 Functions
  • 17.2 Serial Interface Channel 0 Configuration
  • 17.3 Serial Interface Channel 0 Control Registers
  • 17.4 Serial Interface Channel 0 Operations
    • 17.4.1 Operation stop mode
    • 17.4.2 3-wire serial I/O mode operation
    • 17.4.3 2-wire serial I/O mode operation
    • 17.4.4 I2C bus mode operation
    • 17.4.5 Cautions on use of I2C bus mode
    • 17.4.6 Restrictions in I2C bus mode
    • 17.4.7 SCK0#/SCL/P27 pin output manipulation
• CHAPTER 18 SERIAL INTERFACE CHANNEL 1
  • 18.1 Serial Interface Channel 1 Functions
  • 18.2 Serial Interface Channel 1 Configuration
  • 18.3 Serial Interface Channel 1 Control Registers
  • 18.4 Serial Interface Channel 1 Operations
    • 18.4.1 Operation stop mode
    • 18.4.2 3-wire serial I/O mode operation
    • 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function
• CHAPTER 19 SERIAL INTERFACE CHANNEL 2
  • 19.1 Serial Interface Channel 2 Functions
  • 19.2 Serial Interface Channel 2 Configuration
  • 19.3 Serial Interface Channel 2 Control Registers
  • 19.4 Serial Interface Channel 2 Operation
    • 19.4.1 Operation stop mode
    • 19.4.2 Asynchronous serial interface (UART) mode
    • 19.4.3 3-wire serial I/O mode
    • 19.4.4 Limitations when UART mode is used
• CHAPTER 20 REAL-TIME OUTPUT PORT
  • 20.1 Real-Time Output Port Functions
  • 20.2 Real-Time Output Port Configuration
  • 20.3 Real-Time Output Port Control Registers
• CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
  • 21.1 Interrupt Function Types
  • 21.2 Interrupt Sources and Configuration
  • 21.3 Interrupt Function Control Registers
  • 21.4 Interrupt Servicing Operations
    • 21.4.1 Non-maskable interrupt request acknowledge operation
    • 21.4.2 Maskable interrupt request acknowledge operation
    • 21.4.3 Software interrupt request acknowledge operation
    • 21.4.4 Multiple interrupt servicing
    • 21.4.5 Interrupt request reserve
  • 21.5 Test Functions
    • 21.5.1 Registers controlling the test function
    • 21.5.2 Test input signal acknowledge operation
• CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
  • 22.1 External Device Expansion Functions
  • 22.2 External Device Expansion Function Control Register
  • 22.3 External Device Expansion Function Timing
  • 22.4 Example of Connection with Memory
• CHAPTER 23 STANDBY FUNCTION
  • 23.1 Standby Function and Configuration
    • 23.1.1 Standby function
    • 23.1.2 Standby function control register
  • 23.2 Standby Function Operations
    • 23.2.1 HALT mode
    • 23.2.2 STOP mode
• CHAPTER 24 RESET FUNCTION
  • 24.1 Reset Function
• CHAPTER 25 ROM CORRECTION
  • 25.1 ROM Correction Functions
  • 25.2 ROM Correction Configuration
  • 25.3 ROM Correction Control Registers
  • 25.4 ROM Correction Application
  • 25.5 ROM Correction Example
  • 25.6 Program Execution Flow
  • 25.7 Cautions on ROM Correction
• CHAPTER 26 uPD78P054, 78P058
  • 26.1 Memory Size Switching Register (uPD78P054)
  • 26.2 Memory Size Switching Register (uPD78P058)
  • 26.3 Internal Expansion RAM Size Switching Register
  • 26.4 PROM Programming
    • 26.4.1 Operating modes
    • 26.4.2 PROM write procedure
    • 26.4.3 PROM reading procedure
  • 26.5 Erasure Procedure (uPD78P054KK-T and 78P058KK-T Only)
  • 26.6 Opaque Film Masking the Window (uPD78P054KK-T and 78P058KK-T Only)
  • 26.7 Screening of One-Time PROM Versions
• CHAPTER 27 INSTRUCTION SET
  • 27.1 Legends Used in Operation List
    • 27.1.1 Operand identifiers and description methods
    • 27.1.2 Description of "operation" column
    • 27.1.3 Description of "flag operation" column
  • 27.2 Operation List
  • 27.3 Instructions Listed by Addressing Type
• APPENDIX A DIFFERENCES BETWEEN uPD78054, 78054Y SUBSERIES AND uPD78058F, 78058FY SUBSERIES
• APPENDIX B DEVELOPMENT TOOLS
  • B.1 Language Processing Software
  • B.2 PROM Writing Tools
    • B.2.1 Hardware
    • B.2.2 Software
  • B.3 Debugging Tools
    • B.3.1 Hardware
    • B.3.2 Software
  • B.4 OS for IBM PC
  • B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
• APPENDIX C EMBEDDED SOFTWARE
• APPENDIX D REGISTER INDEX
  • D.1 Register Index
• APPENDIX E REVISION HISTORY