Document Outline

• COVER
• INTRODUCTION
• CHAPTER 1 GENERAL
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Pin Configuration (Top View)
  • 1.5 78K/0S Series Lineup
  • 1.6 Block Diagram
  • 1.7 Overview of Functions
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 List of Pin Functions
  • 2.2 Description of Pin Functions
    • 2.2.1 P00 to P07 (Port 0)
    • 2.2.2 P10, P11 (Port 1)
    • 2.2.3 P20 to P25 (Port 2)
    • 2.2.4 P30 to P34 (Port 3)
    • 2.2.5 P50 to P53 (Port 5)
    • 2.2.6 P60 to P67 (Port 6)
    • 2.2.7 P70 to P73 (Port 7)
    • 2.2.8 P80 to P87 (Port 8)
    • 2.2.9 S0 to S27
    • 2.2.10 COM0 to COM3
    • 2.2.11 VLC0 to VLC2
    • 2.2.12 CAPH, CAPL
    • 2.2.13 RESET#
    • 2.2.14 X1, X2
    • 2.2.15 XT1, XT2
    • 2.2.16 AVDD
    • 2.2.17 AVSS
    • 2.2.18 VDD
    • 2.2.19 VSS
    • 2.2.20 VPP (flash memory version only)
    • 2.2.21 IC0 (mask ROM version only)
  • 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Space
    • 3.1.1 Internal program memory space
    • 3.1.2 Internal data memory space
    • 3.1.3 Special function register (SFR) area
    • 3.1.4 Data memory addressing
  • 3.2 Processor Registers
    • 3.2.1 Control registers
    • 3.2.2 General-purpose registers
    • 3.2.3 Special function registers (SFRs)
  • 3.3 Instruction Address Addressing
    • 3.3.1 Relative addressing
    • 3.3.2 Immediate addressing
    • 3.3.3 Table indirect addressing
    • 3.3.4 Register addressing
  • 3.4 Operand Address Addressing
    • 3.4.1 Direct addressing
    • 3.4.2 Short direct addressing
    • 3.4.3 Special function register (SFR) addressing
    • 3.4.4 Register addressing
    • 3.4.5 Register indirect addressing
    • 3.4.6 Based addressing
    • 3.4.7 Stack addressing
• CHAPTER 4 PORT FUNCTIONS
  • 4.1 Port Functions
  • 4.2 Port Configuration
    • 4.2.1 Port 0
    • 4.2.2 Port 1
    • 4.2.3 Port 2
    • 4.2.4 Port 3
    • 4.2.5 Port 5
    • 4.2.6 Port 6
    • 4.2.7 Port 7
    • 4.2.8 Port 8
  • 4.3 Registers Controlling Port Function
  • 4.4 Port Function Operation
    • 4.4.1 Writing to I/O port
    • 4.4.2 Reading from I/O port
    • 4.4.3 Arithmetic operation of I/O port
• CHAPTER 5 CLOCK GENERATOR
  • 5.1 Clock Generator Functions
  • 5.2 Clock Generator Configuration
  • 5.3 Registers Controlling Clock Generator
  • 5.4 System Clock Oscillators
    • 5.4.1 Main system clock oscillator
    • 5.4.2 Subsystem clock oscillator
    • 5.4.3 Example of incorrect resonator connection
    • 5.4.4 Divider circuit
    • 5.4.5 When subsystem clock is not used
    • 5.4.6 Subsystem clock (4 multiplication circuit
  • 5.5 Clock Generator Operation
  • 5.6 Changing Setting of System Clock and CPU Clock
    • 5.6.1 Time required for switching between system clock and CPU clock
    • 5.6.2 Switching between system clock and CPU clock
• CHAPTER 6 16-BIT TIMER 20
  • 6.1 16-Bit Timer 20 Functions
  • 6.2 16-Bit Timer 20 Configuration
  • 6.3 Registers Controlling 16-Bit Timer 20
  • 6.4 16-Bit Timer 20 Operation
    • 6.4.1 Operation as timer interrupt
    • 6.4.2 Operation as timer output
    • 6.4.3 Capture operation
    • 6.4.4 16-bit timer counter 20 readout
  • 6.5 Cautions on Using 16-Bit Timer 20
    • 6.5.1 Restrictions when rewriting 16-bit compare register 20
• CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
  • 7.1 Functions of 8-Bit Timers 50, 60, and 61
  • 7.2 Configuration of 8-Bit Timers 50, 60, and 61
  • 7.3 Control Registers for 8-Bit Timers 50, 60, and 61
  • 7.4 Operation of 8-Bit Timers 50, 60, and 61
    • 7.4.1 Operation as 8-bit timer counter
    • 7.4.2 Operation as 16-bit timer counter
    • 7.4.3 Operation as carrier generator
    • 7.4.4 PWM output mode operation (timer 50)
    • 7.4.5 PPG output mode operation (timer 60 and timer 61)
  • 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61
• CHAPTER 8 WATCH TIMER
  • 8.1 Watch Timer Functions
  • 8.2 Configuration of Watch Timer
  • 8.3 Control Registers for Watch Timer
  • 8.4 Watch Timer Operation
    • 8.4.1 Operation as watch timer
    • 8.4.2 Operation as interval timer
• CHAPTER 9 WATCHDOG TIMER
  • 9.1 Watchdog Timer Functions
  • 9.2 Watchdog Timer Configuration
  • 9.3 Watchdog Timer Control Registers
  • 9.4 Watchdog Timer Operation
    • 9.4.1 Operation as watchdog timer
    • 9.4.2 Operation as interval timer
• CHAPTER 10 10-BIT A/D CONVERTER
  • 10.1 10-Bit A/D Converter Functions
  • 10.2 10-Bit A/D Converter Configuration
  • 10.3 10-Bit A/D Converter Control Registers
  • 10.4 10-Bit A/D Converter Operation
    • 10.4.1 Basic operation of 10-bit A/D converter
    • 10.4.2 Input voltage and conversion result
    • 10.4.3 Operation mode of 10-bit A/D converter
  • 10.5 Cautions Related to 10-Bit A/D Converter
• CHAPTER 11 SERIAL INTERFACE 20
  • 11.1 Serial Interface 20 Functions
  • 11.2 Serial Interface 20 Configuration
  • 11.3 Serial Interface 20 Control Registers
  • 11.4 Serial Interface 20 Operation
    • 11.4.1 Operation stop mode
    • 11.4.2 Asynchronous serial interface (UART) mode
    • 11.4.3 3-wire serial I/O mode
• CHAPTER 12 SERIAL INTERFACE 1A0
  • 12.1 Function of Serial Interface 1A0
  • 12.2 Configuration of Serial Interface 1A0
  • 12.3 Control Registers for Serial Interface 1A0
  • 12.4 Serial Interface 1A0 Operation
    • 12.4.1 Operation stop mode
    • 12.4.2 3-wire serial I/O mode
    • 12.4.3 3-wire serial I/O mode with automatic transmit/receive function
• CHAPTER 13 LCD CONTROLLER/DRIVER
  • 13.1 LCD Controller/Driver Functions
  • 13.2 LCD Controller/Driver Configuration
  • 13.3 Registers Controlling LCD Controller/Driver
  • 13.4 Setting LCD Controller/Driver
  • 13.5 LCD Display Data Memory
  • 13.6 Common and Segment Signals
  • 13.7 Display Modes
    • 13.7.1 Three-time-slice display example
    • 13.7.2 Four-time-slice display example
  • 13.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
• CHAPTER 14 MULTIPLIER
  • 14.1 Multiplier Function
  • 14.2 Multiplier Configuration
  • 14.3 Multiplier Control Register
  • 14.4 Multiplier Operation
• CHAPTER 15 REMOTE CONTROLLER RECEIVER (uPD789489, 78F9489 ONLY)
  • 15.1 Remote Controller Receiver Functions
  • 15.2 Remote Controller Receiver Configuration
  • 15.3 Registers to Control Remote Controller Receiver
  • 15.4 Operation of Remote Controller Receiver
    • 15.4.1 Format of type A reception mode
    • 15.4.2 Operation flow of type A reception mode
    • 15.4.3 Timing
    • 15.4.4 Compare register setting
    • 15.4.5 Error interrupt generation timing
    • 15.4.6 Noise elimination
• CHAPTER 16 INTERRUPT FUNCTIONS
  • 16.1 Interrupt Function Types
  • 16.2 Interrupt Sources and Configuration
  • 16.3 Registers Controlling Interrupt Function
  • 16.4 Interrupt Servicing Operation
    • 16.4.1 Non-maskable interrupt request acknowledgment operation
    • 16.4.2 Maskable interrupt request acknowledgment operation
    • 16.4.3 Multiple interrupt servicing
    • 16.4.4 Putting interrupt requests on hold
• CHAPTER 17 STANDBY FUNCTION
  • 17.1 Standby Function and Configuration
    • 17.1.1 Standby function
    • 17.1.2 Register controlling standby function
  • 17.2 Standby Function Operation
    • 17.2.1 HALT mode
    • 17.2.2 STOP mode
• CHAPTER 18 RESET FUNCTION
• CHAPTER 19 FLASH MEMORY VERSION
  • 19.1 Flash Memory Characteristics
    • 19.1.1 Programming environment
    • 19.1.2 Communication mode
    • 19.1.3 On-board pin processing
    • 19.1.4 Connection of adapter for flash writing
  • 19.2 Cautions on uPD78F9488 and 78F9489
• CHAPTER 20 MASK OPTIONS
• CHAPTER 21 INSTRUCTION SET
  • 21.1 Operation
    • 21.1.1 Operand identifiers and description methods
    • 21.1.2 Description of “Operation” column
    • 21.1.3 Description of “Flag” column
  • 21.2 Operation List
  • 21.3 Instructions Listed by Addressing Type
• CHAPTER 22 ELECTRICAL SPECIFICATIONS (uPD789488, 78F9488, 789489, 78F9489)
• CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)
• CHAPTER 24 PACKAGE DRAWINGS
• CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
• APPENDIX A DEVELOPMENT TOOLS
  • A.1 Software Package
  • A.2 Language Processing Software
  • A.3 Control Software
  • A.4 Flash Memory Writing Tools
  • A.5 Debugging Tools (Hardware)
  • A.6 Debugging Tools (Software)
• APPENDIX B NOTES ON TARGET SYSTEM DESIGN
• APPENDIX C REGISTER INDEX
• APPENDIX D REVISION HISTORY