Document Outline

• Features
• Description
• 1. Pin Configurations and Pinouts
• 2. Block Diagram
• 3. Memory Array
• 4. Device Operation
  • 4.1 Dual-I/O and Quad I/O Operation
• 5. Read Commands
  • 5.1 Continuous Array Read (Legacy Command: E8h Opcode)
  • 5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode)
  • 5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)
  • 5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode)
  • 5.5 Continuous Array Read (Low Power Mode: 01h Opcode)
  • 5.6 Main Memory Page Read (D2h Opcode)
  • 5.7 Buffer Read
  • 5.8 Dual-output Read Array (3Bh Opcode)
  • 5.9 Quad-output Read Array (6Bh Opcode)
• 6. Program and Erase Commands
  • 6.1 Buffer Write
  • 6.2 Dual-input Buffer Write
  • 6.3 Quad-input Buffer Write
  • 6.4 Buffer to Main Memory Page Program with Built-In Erase
  • 6.5 Buffer to Main Memory Page Program without Built-In Erase
  • 6.6 Main Memory Page Program through Buffer with Built-In Erase
  • 6.7 Main Memory Byte/Page Program through Buffer 1 without Built-In Erase
  • 6.8 Page Erase
  • 6.9 Block Erase
  • 6.10 Sector Erase
  • 6.11 Chip Erase
  • 6.12 Program/Erase Suspend
  • 6.13 Program/Erase Resume
• 7. Sector Protection
  • 7.1 Software Sector Protection
    • 7.1.1 Enable Sector Protection
    • 7.1.2 Disable Sector Protection
  • 7.2 Hardware Controlled Protection
  • 7.3 Sector Protection Register
    • 7.3.1 Erase Sector Protection Register
    • 7.3.2 Program Sector Protection Register
    • 7.3.3 Read Sector Protection Register
    • 7.3.4 About the Sector Protection Register
• 8. Security Features
  • 8.1 Sector Lockdown
    • 8.1.1 Read Sector Lockdown Register
    • 8.1.2 Freeze Sector Lockdown
  • 8.2 Security Register
    • 8.2.1 Programming the Security Register
    • 8.2.2 Reading the Security Register
• 9. Additional Commands
  • 9.1 Main Memory Page to Buffer Transfer
  • 9.2 Main Memory Page to Buffer Compare
  • 9.3 Auto Page Rewrite
  • 9.4 Status Register Read
    • 9.4.1 RDY/BUSY Bit
    • 9.4.2 COMP Bit
    • 9.4.3 DENSITY Bits
    • 9.4.4 PROTECT Bit
    • 9.4.5 PAGE SIZE Bit
    • 9.4.6 EPE Bit
    • 9.4.7 SLE Bit
    • 9.4.8 PS2 Bit
    • 9.4.9 PS1 Bit
    • 9.4.10 The ES bit
  • 9.5 Read Configuration Register
    • 9.5.1 QE Bit
  • 9.6 Write Configuration Register
    • 9.6.1 Quad Enable Command
    • 9.6.2 Quad Disable Command
• 10. Deep Power-Down
  • 10.1 Resume from Deep Power-Down
  • 10.2 Ultra-Deep Power-Down
    • 10.2.1 Exit Ultra-Deep Power-Down
• 11. Buffer and Page Size Configuration
• 12. Manufacturer and Device ID Read
• 13. Software Reset
• 14. Operation Mode Summary
  • Group A commands consist of:
  • Group B commands consist of:
  • Group C commands consist of:
  • Group D commands consist of:
• 15. Command Tables
• 16. Power-On/Reset State
  • 16.1 Initial Power-Up Timing Restrictions
• 17. System Considerations
• 18. Electrical Specifications
  • 18.1 Absolute Maximum Ratings*
  • 18.2 DC and AC Operating Range
  • 18.3 DC Characteristics
  • 18.4 AC Characteristics
  • 18.5 Program and Erase Characteristics
• 19. Input Test Waveforms and Measurement Levels
• 20. Output Test Load
• 21. Utilizing the RapidS Function
• 22. AC Waveforms
• 23. Write Operations
• 24. Read Operations
• 25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3
• 26. Auto Page Rewrite Flowchart
• 27. Ordering Information
  • 27.1 Ordering Detail
  • 27.2 Ordering Codes
  • 27.3 Ordering Codes (Binary Page Mode)
  • 27.4 8S2 – 8-lead EIAJ SOIC
  • 27.5 8MA1 – 8-pad UDFN
  • 27.6 9CC1 – 9-ball UBGA
• 28. Revision History