Document Outline

• Features
• Pin Configuration
• Description
  • Pin Descriptions
    • VCC
    • GND
    • Port B (PB7..PB0)
    • Port D (PD6..PD0)
    • RESET
    • XTAL1
    • XTAL2
  • Crystal Oscillator
• Architectural Overview
  • General Purpose Register File
    • X-register, Y-register, and Z- register
  • ALU – Arithmetic Logic Unit
  • In-System Programmable Flash Program Memory
  • EEPROM Data Memory
  • SRAM Data Memory
  • Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Data Direct
    • Data Indirect with Displacement
    • Data Indirect
    • Data Indirect with Pre- decrement
    • Data Indirect with Post- increment
    • Constant Addressing Using the LPM Instruction
    • Indirect Program Addressing, IJMP and ICALL
    • Relative Program Addressing, RJMP and RCALL
  • Memory Access and Instruction Execution Timing
  • I/O Memory
    • Status Register – SREG
    • Stack Pointer – SP
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-on Reset
    • External Reset
    • Watchdog Reset
    • Interrupt Handling
    • General Interrupt Mask Register – GIMSK
    • General Interrupt FLAG Register – GIFR
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt FLAG Register – TIFR
    • External Interrupts
    • Interrupt Response Time
    • MCU Control Register – MCUCR
  • Sleep Modes
    • Idle Mode
    • Power-down Mode
• Timer/Counters
  • Timer/Counter Prescaler
  • 8-bit Timer/Counter0
    • Timer/Counter0 Control Register – TCCR0
    • Timer/Counter0 – TCNT0
  • 16-bit Timer/Counter1
    • Timer/Counter1 Control Register A – TCCR1A
    • Timer/Counter1 Control Register B – TCCR1B
    • Timer/Counter1 – TCNT1H and TCNT1L
    • Timer/Counter1 Output Compare Register A – OCR1AH and OCR1AL
    • Timer/Counter1 Input Capture Register – ICR1H and ICR1L
    • Timer/Counter1 in PWM Mode
• Watchdog Timer
  • Watchdog Timer Control Register – WDTCR
• EEPROM Read/Write Access
  • EEPROM Address Register – EEAR
  • EEPROM Data Register – EEDR
  • EEPROM Control Register – EECR
  • Prevent EEPROM Corruption
• UART
  • Data Transmission
  • Data Reception
  • UART Control
    • The UART I/O Data Register – UDR
    • UART Status Register – USR
    • UART Control Register – UCR
    • Baud Rate Generator
    • UART Baud Rate Register – UBRR
• Analog Comparator
  • Analog Comparator Control and Status Register – ACSR
• I/O Ports
  • Port B
    • Port B Data Register – PORTB
    • Port B Data Direction Register – DDRB
    • Port B Input Pins Address – PINB
    • Port B as General Digital I/O
    • Alternate Functions of Port B
    • Port B Schematics
  • Port D
    • Port D Data Register – PORTD
    • Port D Data Direction Register – DDRD
    • Port D Input Pins Address – PIND
    • Port D as General Digital I/O
    • Alternate Functions of Port D
    • Port D Schematics
• Memory Programming
  • Program and Data Memory Lock Bits
  • Fuse Bits
  • Signature Bytes
  • Programming the Flash and EEPROM
  • Parallel Programming
    • Signal Names
    • Enter Programming Mode
    • Chip Erase
    • Programming the Flash
    • Reading the Flash
    • Programming the EEPROM
    • Reading the EEPROM
    • Programming the Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
  • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling EEPROM
    • Data Polling Flash
  • Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • DC Characteristics
  • External Clock Drive Waveforms
  • External Clock Drive
• Typical Characteristics
• Register Summary
• Instruction Set Summary
• Ordering Information
• Packaging Information
  • 20P3
  • 20S
• Table of Contents