Document Outline

• Ordering Information
• Features
  • Pin Configuration
• Description
  • Block Diagram
  • Comparison Between ATmega603 and ATmega103
  • Pin Descriptions
    • VCC
    • GND
    • Port A (PA7..PA0)
    • Port B (PB7..PB0)
    • Port C (PC7..PC0)
    • Port D (PD7..PD0)
    • Port E (PE7..PE0)
    • Port F (PF7..PF0)
    • RESET
    • XTAL1
    • XTAL2
    • TOSC1
    • TOSC2
    • WR
    • RD
    • ALE
    • AVCC
    • AREF
    • AGND
    • PEN
  • Clock Options
    • Crystal Oscillator
    • External Clock
    • Timer Oscillator
• Architectural Overview
  • General Purpose Register File
    • X-register, Y-register and Z-register
  • ALU - Arithmetic Logic Unit
  • ISP Flash Program Memory
  • SRAM Data Memory
  • Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Data Direct
    • Data Indirect with Displacement
    • Data Indirect
    • Data Indirect With Pre-Decrement
    • Data Indirect With Post-Increment
    • Constant Addressing Using the LPM and ELPM Instructions
    • Direct Program Address, JMP and CALL
    • Indirect Program Addressing, IJMP and ICALL
    • Relative Program Addressing, RJMP and RCALL
  • EEPROM Data Memory
  • Memory Access Times and Instruction Execution Timing
  • I/O Memory
    • Status Register - SREG
    • Stack Pointer - SP
    • RAM Page Z Select Register - RAMPZ
    • MCU Control Register - MCUCR
    • XTAL Divide Control Register - XDIV
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-On Reset
    • External Reset
    • Watchdog Reset
    • MCU Status Register - MCUSR
    • Interrupt Handling
    • External Interrupt Mask Register - EIMSK
    • External Interrupt Flag Register - EIFR
    • External Interrupt Control Register - EICR
    • Timer/Counter Interrupt Mask Register - TIMSK
    • Timer/Counter Interrupt Flag Register - TIFR
    • Interrupt Response Time
  • Sleep Modes
    • Idle Mode
    • Power Down Mode
    • Power Save Mode
• Timer/Counters
  • Timer/Counter Prescalers
  • 8-bit Timer/Counters T/C0 and T/C2
    • Timer/Counter0 Control Register - TCCR0
    • Timer/Counter2 Control Register - TCCR2
    • Timer/Counter0 - TCNT0
    • Timer/Counter2 - TCNT2
    • Timer/Counter0 Output Compare Register - OCR0
    • Timer/Counter2 Output Compare Register - OCR2
    • Timer/Counter 0 and 2 in PWM mode
    • Asynchronous Status Register - ASSR
    • Asynchronous Operation of Timer/Counter0
  • 16-bit Timer/Counter1
    • Timer/Counter1 Control Register A - TCCR1A
    • Timer/Counter1 Control Register B - TCCR1B
    • Timer/Counter1 - TCNT1H and TCNT1L
    • Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
    • Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
    • Timer/Counter1 Input Capture Register - ICR1H and ICR1L
    • Timer/Counter1 in PWM mode
• Watchdog Timer
  • Watchdog Timer Control Register - WDTCR
• EEPROM Read/Write Access
  • EEPROM Address Register - EEARH, EEARL
  • EEPROM Data Register - EEDR
  • EEPROM Control Register - EECR
  • Prevent EEPROM Corruption
• Serial Peripheral Interface - SPI
  • SS Pin Functionality
  • Data Modes
    • SPI Control Register - SPCR
    • SPI Status Register - SPSR
    • SPI Data Register - SPDR
• UART
  • Data Transmission
  • Data Reception
  • UART Control
    • UART I/O Data Register - UDR
    • UART Status Register - USR
    • UART Control Register - UCR
    • Baud Rate Generator
    • UART Baud Rate Register - UBRR
• Analog Comparator
  • Analog Comparator Control and Status Register - ACSR
• Analog to Digital Converter
  • Operation
  • Prescaling
  • ADC Noise Canceler Function
    • ADC Multiplexer Select Register - ADMUX
    • ADC Control and Status Register - ADCSR
    • ADC Data Register - ADCL and ADCH
  • ADC Noise Canceling Techniques
  • ADC DC Characteristics
• Interface to external SRAM
• I/O-Ports
  • Port A
    • Port A Data Register - PORTA
    • Port A Data Direction Register - DDRA
    • Port A Input Pins Address - PINA
    • Port A as General Digital I/O
    • Port A Schematics
  • Port B
    • Port B Data Register - PORTB
    • Port B Data Direction Register - DDRB
    • Port B Input Pins Address - PINB
    • Port B as General Digital I/O
    • Alternate Functions of Port B
    • Port B Schematics
  • Port C
    • The Port C Data Register - PORTC
    • Port C Schematics
  • Port D
    • Port D Data Register - PORTD
    • Port D Data Direction Register - DDRD
    • Port D Input Pins Address - PIND
    • Port D as general digital I/O
    • Alternate Functions of Port D
    • INT0 .. INT3 - Port D, Bits 0..3
    • IC1 - Port D, Bit 4
    • T1 - Port D, Bit 6
    • T2 - Port D, Bit 7
    • Port D Schematics
  • Port E
    • Port E Data Register - PORTE
    • Port E Data Direction Register - DDRE
    • Port E Input Pins Address - PINE
    • Port E as general digital I/O
    • Alternate Functions OF Port E
    • PDI/RXD - Port E, Bit 0
    • PDO/TXD - Port E, Bit 1
    • AC+ - Port E, Bit 2
    • AC- - Port E, Bit 3
    • INT4 .. INT7 - Port E, Bit 4-7
    • Port E Schematics
  • Port F
    • Port F Input Pins Address - PINF
• Memory Programming
  • Program and Data Memory Lock Bits
  • Fuse Bits
  • Signature Bytes
  • Programming the Flash and EEPROM
  • Parallel Programming
    • Signal Names
    • Enter Programming Mode
    • Chip Erase
    • Programming The Flash
    • Programming The EEPROM
    • Reading The Flash
    • Reading The EEPROM
    • Programming The Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
  • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling for the EEPROM
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • DC Characteristics (Continued)
  • External Data Memory Timing
  • External Clock Drive Waveforms
• Typical characteristics
• Register Summary
• Instruction Set Summary (Continued)