Document Outline

• Features
• 1. Pin Configurations
  • 1.1 Pin Description
    • 1.1.1 VCC
    • 1.1.2 GND
    • 1.1.3 Port B (PB3..PB0)
    • 1.1.4 RESET
• 2. Overview
  • 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10
• 3. General Information
  • 3.1 Resources
  • 3.2 Code Examples
  • 3.3 Data Retention
  • 3.4 Disclaimer
• 4. CPU Core
  • 4.1 Architectural Overview
  • 4.2 ALU – Arithmetic Logic Unit
  • 4.3 Status Register
  • 4.4 General Purpose Register File
    • 4.4.1 The X-register, Y-register, and Z-register
  • 4.5 Stack Pointer
  • 4.6 Instruction Execution Timing
  • 4.7 Reset and Interrupt Handling
    • 4.7.1 Interrupt Response Time
  • 4.8 Register Description
    • 4.8.1 CCP – Configuration Change Protection Register
    • 4.8.2 SPH and SPL — Stack Pointer Register
    • 4.8.3 SREG – Status Register
• 5. Memories
  • 5.1 In-System Re-programmable Flash Program Memory
  • 5.2 Data Memory
    • 5.2.1 Data Memory Access Times
  • 5.3 I/O Memory
• 6. Clock System
  • 6.1 Clock Subsystems
    • 6.1.1 CPU Clock – clkCPU
    • 6.1.2 I/O Clock – clkI/O
    • 6.1.3 NVM clock - clkNVM
    • 6.1.4 ADC Clock – clkADC
  • 6.2 Clock Sources
    • 6.2.1 Calibrated Internal 8 MHz Oscillator
    • 6.2.2 External Clock
    • 6.2.3 Internal 128 kHz Oscillator
    • 6.2.4 Switching Clock Source
    • 6.2.5 Default Clock Source
  • 6.3 System Clock Prescaler
    • 6.3.1 Switching Prescaler Setting
  • 6.4 Starting
    • 6.4.1 Starting from Reset
    • 6.4.2 Starting from Power-Down Mode
    • 6.4.3 Starting from Idle / ADC Noise Reduction / Standby Mode
  • 6.5 Register Description
    • 6.5.1 CLKMSR – Clock Main Settings Register
    • 6.5.2 OSCCAL – Oscillator Calibration Register
    • 6.5.3 CLKPSR – Clock Prescale Register
• 7. Power Management and Sleep Modes
  • 7.1 Sleep Modes
    • 7.1.1 Idle Mode
    • 7.1.2 ADC Noise Reduction Mode
    • 7.1.3 Power-down Mode
    • 7.1.4 Standby Mode
  • 7.2 Power Reduction Register
  • 7.3 Minimizing Power Consumption
    • 7.3.1 Analog Comparator
    • 7.3.2 Analog to Digital Converter
    • 7.3.3 Watchdog Timer
    • 7.3.4 Port Pins
  • 7.4 Register Description
    • 7.4.1 SMCR – Sleep Mode Control Register
    • 7.4.2 PRR – Power Reduction Register
• 8. System Control and Reset
  • 8.1 Resetting the AVR
  • 8.2 Reset Sources
    • 8.2.1 Power-on Reset
    • 8.2.2 VCC Level Monitoring
    • 8.2.3 External Reset
    • 8.2.4 Watchdog Reset
  • 8.3 Watchdog Timer
    • 8.3.1 Procedure for Changing the Watchdog Timer Configuration
      • 8.3.1.1 Safety Level 1
      • 8.3.1.2 Safety Level 2
    • 8.3.2 Code Examples
  • 8.4 Register Description
    • 8.4.1 WDTCSR – Watchdog Timer Control and Status Register
    • 8.4.2 VLMCSR – VCC Level Monitoring Control and Status register
    • 8.4.3 RSTFLR – Reset Flag Register
• 9. Interrupts
  • 9.1 Interrupt Vectors
  • 9.2 External Interrupts
    • 9.2.1 Low Level Interrupt
    • 9.2.2 Pin Change Interrupt Timing
  • 9.3 Register Description
    • 9.3.1 EICRA – External Interrupt Control Register A
    • 9.3.2 EIMSK – External Interrupt Mask Register
    • 9.3.3 EIFR – External Interrupt Flag Register
    • 9.3.4 PCICR – Pin Change Interrupt Control Register
    • 9.3.5 PCIFR – Pin Change Interrupt Flag Register
    • 9.3.6 PCMSK – Pin Change Mask Register
• 10. I/O Ports
  • 10.1 Overview
  • 10.2 Ports as General Digital I/O
    • 10.2.1 Configuring the Pin
    • 10.2.2 Toggling the Pin
    • 10.2.3 Break-Before-Make Switching
    • 10.2.4 Reading the Pin Value
    • 10.2.5 Digital Input Enable and Sleep Modes
    • 10.2.6 Unconnected Pins
    • 10.2.7 Program Example
  • 10.3 Alternate Port Functions
    • 10.3.1 Alternate Functions of Port B
  • 10.4 Register Description
    • 10.4.1 PORTCR – Port Control Register
    • 10.4.2 PUEB – Port B Pull-up Enable Control Register
    • 10.4.3 PORTB – Port B Data Register
    • 10.4.4 DDRB – Port B Data Direction Register
    • 10.4.5 PINB – Port B Input Pins
• 11. 16-bit Timer/Counter0
  • 11.1 Features
  • 11.2 Overview
    • 11.2.1 Registers
    • 11.2.2 Definitions
  • 11.3 Clock Sources
    • 11.3.1 Prescaler
      • 11.3.1.1 Prescaler Reset
    • 11.3.2 External Clock Source
  • 11.4 Counter Unit
  • 11.5 Input Capture Unit
    • 11.5.1 Input Capture Trigger Source
    • 11.5.2 Noise Canceler
    • 11.5.3 Using the Input Capture Unit
  • 11.6 Output Compare Units
    • 11.6.1 Force Output Compare
    • 11.6.2 Compare Match Blocking by TCNT0 Write
    • 11.6.3 Using the Output Compare Unit
  • 11.7 Compare Match Output Unit
    • 11.7.1 Compare Output Mode and Waveform Generation
  • 11.8 Modes of Operation
    • 11.8.1 Normal Mode
    • 11.8.2 Clear Timer on Compare Match (CTC) Mode
    • 11.8.3 Fast PWM Mode
    • 11.8.4 Phase Correct PWM Mode
    • 11.8.5 Phase and Frequency Correct PWM Mode
  • 11.9 Timer/Counter Timing Diagrams
  • 11.10 Accessing 16-bit Registers
    • 11.10.1 Reusing the Temporary High Byte Register
  • 11.11 Register Description
    • 11.11.1 TCCR0A – Timer/Counter0 Control Register A
    • 11.11.2 TCCR0B – Timer/Counter0 Control Register B
    • 11.11.3 TCCR0C – Timer/Counter0 Control Register C
    • 11.11.4 TCNT0H and TCNT0L – Timer/Counter0
    • 11.11.5 OCR0AH and OCR0AL – Output Compare Register 0 A
    • 11.11.6 OCR0BH and OCR0BL – Output Compare Register 0 B
    • 11.11.7 ICR0H and ICR0L – Input Capture Register 0
    • 11.11.8 TIMSK0 – Timer/Counter Interrupt Mask Register 0
    • 11.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0
    • 11.11.10 GTCCR – General Timer/Counter Control Register
• 12. Analog Comparator
  • 12.1 Register Description
    • 12.1.1 ACSR – Analog Comparator Control and Status Register
    • 12.1.2 DIDR0 – Digital Input Disable Register 0
• 13. Analog to Digital Converter
  • 13.1 Features
  • 13.2 Overview
  • 13.3 Operation
  • 13.4 Starting a Conversion
  • 13.5 Prescaling and Conversion Timing
  • 13.6 Changing Channel
    • 13.6.1 ADC Input Channels
    • 13.6.2 ADC Voltage Reference
  • 13.7 ADC Noise Canceler
  • 13.8 Analog Input Circuitry
  • 13.9 Noise Canceling Techniques
  • 13.10 ADC Accuracy Definitions
  • 13.11 ADC Conversion Result
  • 13.12 Register Description
    • 13.12.1 ADMUX – ADC Multiplexer Selection Register
    • 13.12.2 ADCSRA – ADC Control and Status Register A
    • 13.12.3 ADCSRB – ADC Control and Status Register B
    • 13.12.4 ADCL – ADC Data Register
    • 13.12.5 DIDR0 – Digital Input Disable Register 0
• 14. Programming interface
  • 14.1 Features
  • 14.2 Overview
  • 14.3 Physical Layer of Tiny Programming Interface
    • 14.3.1 Enabling
    • 14.3.2 Disabling
    • 14.3.3 Frame Format
    • 14.3.4 Parity Bit Calculation
    • 14.3.5 Supported Characters
    • 14.3.6 Operation
    • 14.3.7 Serial Data Reception
    • 14.3.8 Serial Data Transmission
    • 14.3.9 Collision Detection Exception
    • 14.3.10 Direction Change
  • 14.4 Access Layer of Tiny Programming Interface
    • 14.4.1 Message format
    • 14.4.2 Exception Handling and Synchronisation
  • 14.5 Instruction Set
    • 14.5.1 SLD - Serial LoaD from data space using indirect addressing
    • 14.5.2 SST - Serial STore to data space using indirect addressing
    • 14.5.3 SSTPR - Serial STore to Pointer Register
    • 14.5.4 SIN - Serial IN from i/o space using direct addressing
    • 14.5.5 SOUT - Serial OUT to i/o space using direct addressing
    • 14.5.6 SLDCS - Serial LoaD data from Control and Status space using direct addressing
    • 14.5.7 SSTCS - Serial STore data to Control and Status space using direct addressing
    • 14.5.8 SKEY - Serial KEY signaling
  • 14.6 Accessing the Non-Volatile Memory Controller
  • 14.7 Control and Status Space Register Descriptions
    • 14.7.1 TPIIR – Tiny Programming Interface Identification Register
    • 14.7.2 TPIPCR – Tiny Programming Interface Physical Layer Control Register
    • 14.7.3 TPISR – Tiny Programming Interface Status Register
• 15. Memory Programming
  • 15.1 Features
  • 15.2 Overview
  • 15.3 Non-Volatile Memories
    • 15.3.1 Non-Volatile Memory Lock Bits
    • 15.3.2 Flash Memory
    • 15.3.3 Configuration Section
      • 15.3.3.1 Latching of Configuration Bits
    • 15.3.4 Signature Section
    • 15.3.5 Calibration Section
      • 15.3.5.1 Latching of Calibration Value
  • 15.4 Accessing the NVM
    • 15.4.1 Addressing the Flash
    • 15.4.2 Reading the Flash
    • 15.4.3 Programming the Flash
      • 15.4.3.1 Chip Erase
      • 15.4.3.2 Erasing the Code Section
      • 15.4.3.3 Writing a Code Word
      • 15.4.3.4 Erasing the Configuration Section
      • 15.4.3.5 Writing a Configuration Word
    • 15.4.4 Reading NVM Lock Bits
    • 15.4.5 Writing NVM Lock Bits
  • 15.5 Self programming
  • 15.6 External Programming
    • 15.6.1 Entering External Programming Mode
    • 15.6.2 Exiting External Programming Mode
  • 15.7 Register Description
    • 15.7.1 NVMCSR - Non-Volatile Memory Control and Status Register
    • 15.7.2 NVMCMD - Non-Volatile Memory Command Register
• 16. Electrical Characteristics
  • 16.1 Absolute Maximum Ratings*
  • 16.2 DC Characteristics
  • 16.3 Speed Grades
  • 16.4 Clock Characteristics
    • 16.4.1 Accuracy of Calibrated Internal Oscillator
    • 16.4.2 External Clock Drive
  • 16.5 System and Reset Characteristics
    • 16.5.1 Power-On Reset
    • 16.5.2 VCC Level Monitor
  • 16.6 Analog Comparator Characteristics
  • 16.7 ADC Characteristics (ATtiny5/10, only) – Preliminary Data
  • 16.8 Serial Programming Characteristics
• 17. Typical Characteristics
  • 17.1 Supply Current of I/O Modules
  • 17.2 ATtiny4/5/9/10
    • 17.2.1 Active Supply Current
    • 17.2.2 Idle Supply Current
    • 17.2.3 Power-down Supply Current
    • 17.2.4 Pin Pull-up
    • 17.2.5 Pin Driver Strength
    • 17.2.6 Pin Threshold and Hysteresis
    • 17.2.7 Analog Comparator Offset
    • 17.2.8 Internal Oscillator Speed
    • 17.2.9 VLM Thresholds
    • 17.2.10 Current Consumption of Peripheral Units
    • 17.2.11 Current Consumption in Reset and Reset Pulsewidth
• 18. Register Summary
• 19. Instruction Set Summary
• 20. Ordering Information
  • 20.1 ATtiny4
  • 20.2 ATtiny5
  • 20.3 ATtiny9
  • 20.4 ATtiny10
• 21. Packaging Information
  • 21.1 6ST1
• 22. Errata
  • 22.1 ATtiny4
    • 22.1.1 Rev. C
    • 22.1.2 Rev. A – B
  • 22.2 ATtiny5
    • 22.2.1 Rev. C
    • 22.2.2 Rev. A – B
  • 22.3 ATtiny9
    • 22.3.1 Rev. C
    • 22.3.2 Rev. A – B
  • 22.4 ATtiny10
    • 22.4.1 Rev. C
    • 22.4.2 Rev. A – B
• 23. Datasheet Revision History
  • 23.1 Rev. 8127B – 08/09
  • 23.2 Rev. 8127A – 04/09
• Table of Contents