Document Outline

• Features
• 1. Pin Configurations
  • 1.1 Disclaimer
• 2. Overview
  • 2.1 Block Diagram
  • 2.2 Pin Descriptions
    • 2.2.1 VCC
    • 2.2.2 GND
    • 2.2.3 AVCC
    • 2.2.4 AGND
    • 2.2.5 Port A (PA7..PA0)
    • 2.2.6 Port B (PB7..PB0)
    • 2.2.7 RESET
• 3. Resources
• 4. About Code Examples
• 5. AVR CPU Core
  • 5.1 Overview
  • 5.2 ALU - Arithmetic Logic Unit
  • 5.3 Status Register
    • 5.3.1 SREG - AVR Status Register
  • 5.4 General Purpose Register File
    • 5.4.1 The X-register, Y-register, and Z-register
  • 5.5 Stack Pointer
    • 5.5.1 SPH and SPL - Stack Pointer Register
  • 5.6 Instruction Execution Timing
  • 5.7 Reset and Interrupt Handling
    • 5.7.1 Interrupt Response Time
• 6. AVR Memories
  • 6.1 In-System Re-programmable Flash Program Memory
  • 6.2 SRAM Data Memory
    • 6.2.1 Data Memory Access Times
  • 6.3 EEPROM Data Memory
    • 6.3.1 EEPROM Read/Write Access
    • 6.3.2 Atomic Byte Programming
    • 6.3.3 Split Byte Programming
    • 6.3.4 Erase
    • 6.3.5 Write
    • 6.3.6 Preventing EEPROM Corruption
  • 6.4 I/O Memory
    • 6.4.1 General Purpose I/O Registers
  • 6.5 Register Description
    • 6.5.1 EEARH and EEARL - EEPROM Address Register
    • 6.5.2 EEDR - EEPROM Data Register
    • 6.5.3 EECR - EEPROM Control Register
    • 6.5.4 GPIOR2 - General Purpose I/O Register 2
    • 6.5.5 GPIOR1 - General Purpose I/O Register 1
    • 6.5.6 GPIOR0 - General Purpose I/O Register 0
• 7. System Clock and Clock Options
  • 7.1 Clock Systems and their Distribution
    • 7.1.1 CPU Clock - clkCPU
    • 7.1.2 I/O Clock - clkI/O
    • 7.1.3 Flash Clock - clkFLASH
    • 7.1.4 ADC Clock - clkADC
    • 7.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK
  • 7.2 Clock Sources
  • 7.3 Default Clock Source
  • 7.4 External Clock
  • 7.5 High Frequency PLL Clock - PLLCLK
  • 7.6 Calibrated Internal RC Oscillator
  • 7.7 128 kHz Internal Oscillator
  • 7.8 Low-frequency Crystal Oscillator
  • 7.9 Crystal Oscillator
  • 7.10 Clock Output Buffer
  • 7.11 System Clock Prescaler
    • 7.11.1 Switching Time
  • 7.12 Register Description
    • 7.12.1 OSCCAL - Oscillator Calibration Register
    • 7.12.2 CLKPR - Clock Prescale Register
• 8. Power Management and Sleep Modes
  • 8.1 Sleep Modes
  • 8.2 Idle Mode
  • 8.3 ADC Noise Reduction Mode
  • 8.4 Power-down Mode
  • 8.5 Standby Mode
  • 8.6 Power Reduction Register
  • 8.7 Minimizing Power Consumption
    • 8.7.1 Analog to Digital Converter
    • 8.7.2 Analog Comparator
    • 8.7.3 Brown-out Detector
    • 8.7.4 Internal Voltage Reference
    • 8.7.5 Watchdog Timer
    • 8.7.6 Port Pins
  • 8.8 Register Description
    • 8.8.1 MCUCR - MCU Control Register
    • 8.8.2 PRR - Power Reduction Register
• 9. System Control and Reset
  • 9.0.1 Resetting the AVR
  • 9.0.2 Reset Sources
  • 9.0.3 Power-on Reset
  • 9.0.4 External Reset
  • 9.0.5 Brown-out Detection
  • 9.0.6 Watchdog Reset
  • 9.1 Internal Voltage Reference
    • 9.1.1 Voltage Reference Enable Signals and Start-up Time
  • 9.2 Watchdog Timer
  • 9.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
    • 9.3.1 Safety Level 1
    • 9.3.2 Safety Level 2
  • 9.4 Register Description
    • 9.4.1 MCUSR - MCU Status Register
    • 9.4.2 WDTCR - Watchdog Timer Control Register
• 10. Interrupts
  • 10.1 Interrupt Vectors in ATtiny261/461/861
• 11. External Interrupts
  • 11.1 Register Description
    • 11.1.1 MCUCR - MCU Control Register
    • 11.1.2 GIMSK - General Interrupt Mask Register
    • 11.1.3 GIFR - General Interrupt Flag Register
    • 11.1.4 PCMSK0 - Pin Change Mask Register A
    • 11.1.5 PCMSK1 - Pin Change Mask Register B
• 12. I/O Ports
  • 12.1 Overview
  • 12.2 Ports as General Digital I/O
    • 12.2.1 Configuring the Pin
    • 12.2.2 Toggling the Pin
    • 12.2.3 Switching Between Input and Output
    • 12.2.4 Reading the Pin Value
    • 12.2.5 Digital Input Enable and Sleep Modes
    • 12.2.6 Unconnected Pins
  • 12.3 Alternate Port Functions
    • 12.3.1 Alternate Functions of Port B
    • 12.3.2 Alternate Functions of Port A
  • 12.4 Register Description
    • 12.4.1 MCUCR - MCU Control Register
    • 12.4.2 PORTA - Port A Data Register
    • 12.4.3 DDRA - Port A Data Direction Register
    • 12.4.4 PINA - Port A Input Pins Address
    • 12.4.5 PORTB - Port B Data Register
    • 12.4.6 DDRB - Port B Data Direction Register
    • 12.4.7 PINB - Port B Input Pins Address
• 13. Timer/Counter0 Prescaler
  • 13.0.1 Prescaler Reset
  • 13.0.2 External Clock Source
  • 13.1 Register Description
    • 13.1.1 TCCR0B - Timer/Counter0 Control Register B
• 14. Timer/Counter0
  • 14.1 Features
  • 14.2 Overview
    • 14.2.1 Registers
    • 14.2.2 Definitions
  • 14.3 Timer/Counter Clock Sources
  • 14.4 Counter Unit
  • 14.5 Modes of Operation
    • 14.5.1 Normal 8-bit Mode
    • 14.5.2 Clear Timer on Compare Match (CTC) 8-bit Mode
    • 14.5.3 16-bit Mode
    • 14.5.4 8-bit Input Capture Mode
    • 14.5.5 16-bit Input Capture Mode
  • 14.6 Input Capture Unit
    • 14.6.1 Input Capture Trigger Source
    • 14.6.2 Noise Canceler
    • 14.6.3 Using the Input Capture Unit
  • 14.7 Output Compare Unit
    • 14.7.1 Compare Match Blocking by TCNT0 Write
    • 14.7.2 Using the Output Compare Unit
  • 14.8 Timer/Counter Timing Diagrams
  • 14.9 Accessing Registers in 16-bit Mode
    • 14.9.1 Reusing the temporary high byte register
  • 14.10 Register Description
    • 14.10.1 TCCR0A - Timer/Counter0 Control Register A
    • 14.10.2 TCNT0L - Timer/Counter0 Register Low Byte
    • 14.10.3 TCNT0H - Timer/Counter0 Register High Byte
    • 14.10.4 OCR0A - Timer/Counter0 Output Compare Register A
    • 14.10.5 OCR0B - Timer/Counter0 Output Compare Register B
    • 14.10.6 TIMSK - Timer/Counter0 Interrupt Mask Register
    • 14.10.7 TIFR - Timer/Counter0 Interrupt Flag Register
• 15. Timer/Counter1 Prescaler
  • 15.0.1 Prescaler Reset
  • 15.0.2 Prescaler Initialization for Asynchronous Mode
  • 15.1 Register Description
    • 15.1.1 PLLCSR - PLL Control and Status Register
    • 15.1.2 TCCR1B - Timer/Counter1 Control Register B
• 16. Timer/Counter1
  • 16.1 Features
  • 16.2 Overview
    • 16.2.1 Speed
    • 16.2.2 Accuracy
    • 16.2.3 Registers
    • 16.2.4 Synchronization
    • 16.2.5 Definitions
  • 16.3 Counter Unit
    • 16.3.1 Counter Initialization for Asynchronous Mode
  • 16.4 Output Compare Unit
    • 16.4.1 Force Output Compare
    • 16.4.2 Compare Match Blocking by TCNT1 Write
    • 16.4.3 Using the Output Compare Unit
  • 16.5 Dead Time Generator
  • 16.6 Compare Match Output Unit
    • 16.6.1 Compare Output Mode and Waveform Generation
  • 16.7 Modes of Operation
    • 16.7.1 Normal Mode
    • 16.7.2 IFast PWM Mode
    • 16.7.3 Phase and Frequency Correct PWM Mode
    • 16.7.4 PWM6 Mode
  • 16.8 Timer/Counter Timing Diagrams
  • 16.9 Fault Protection Unit
    • 16.9.1 Fault Protection Trigger Source
    • 16.9.2 Noise Canceler
  • 16.10 Accessing 10-Bit Registers
    • 16.10.1 Reusing the temporary high byte register
  • 16.11 Register Description
    • 16.11.1 TCCR1A - Timer/Counter1 Control Register A
    • 16.11.2 TCCR1B - Timer/Counter1 Control Register B
    • 16.11.3 TCCR1C - Timer/Counter1 Control Register C
    • 16.11.4 TCCR1D - Timer/Counter1 Control Register D
    • 16.11.5 TCCR1E - Timer/Counter1 Control Register E
    • 16.11.6 TCNT1 - Timer/Counter1
    • 16.11.7 TC1H - Timer/Counter1 High Byte
    • 16.11.8 OCR1A - Timer/Counter1 Output Compare Register A
    • 16.11.9 OCR1B - Timer/Counter1 Output Compare Register B
    • 16.11.10 OCR1C - Timer/Counter1 Output Compare Register C
    • 16.11.11 OCR1D - Timer/Counter1 Output Compare Register D
    • 16.11.12 TIMSK - Timer/Counter1 Interrupt Mask Register
    • 16.11.13 TIFR - Timer/Counter1 Interrupt Flag Register
    • 16.11.14 DT1 - Timer/Counter1 Dead Time Value
• 17. USI - Universal Serial Interface
  • 17.1 Features
  • 17.2 Overview
  • 17.3 Functional Descriptions
    • 17.3.1 Three-wire Mode
    • 17.3.2 SPI Master Operation Example
    • 17.3.3 SPI Slave Operation Example
    • 17.3.4 Two-wire Mode
    • 17.3.5 Start Condition Detector
  • 17.4 Alternative USI Usage
    • 17.4.1 Half-duplex Asynchronous Data Transfer
    • 17.4.2 4-bit Counter
    • 17.4.3 12-bit Timer/Counter
    • 17.4.4 Edge Triggered External Interrupt
    • 17.4.5 Software Interrupt
  • 17.5 Register Descriptions
    • 17.5.1 USIDR - USI Data Register
    • 17.5.2 USIBR - USI Buffer Register
    • 17.5.3 USISR - USI Status Register
    • 17.5.4 USICR - USI Control Register
    • 17.5.5 USIPP - USI Pin Position
• 18. AC - Analog Comparator
  • 18.1 Register Description
    • 18.1.1 ACSRA - Analog Comparator Control and Status Register A
  • 18.2 Analog Comparator Multiplexed Input
    • 18.2.1 ACSRB - Analog Comparator Control and Status Register B
• 19. ADC - Analog to Digital Converter
  • 19.1 Features
  • 19.2 Overview
  • 19.3 Operation
  • 19.4 Starting a Conversion
  • 19.5 Prescaling and Conversion Timing
  • 19.6 Changing Channel or Reference Selection
    • 19.6.1 ADC Input Channels
    • 19.6.2 ADC Voltage Reference
  • 19.7 ADC Noise Canceler
    • 19.7.1 Analog Input Circuitry
    • 19.7.2 Analog Noise Canceling Techniques
    • 19.7.3 ADC Accuracy Definitions
  • 19.8 ADC Conversion Result
    • 19.8.1 Single Ended Conversion
    • 19.8.2 Unipolar Differential Conversion
    • 19.8.3 Bipolar Differential Conversion
  • 19.9 Temperature Measurement
  • 19.10 Register Descriptin
    • 19.10.1 ADMUX - ADC Multiplexer Selection Register
    • 19.10.2 ADCSRA - ADC Control and Status Register A
    • 19.10.3 ADCL and ADCH - The ADC Data Register
      • 19.10.3.1 ADLAR = 0
      • 19.10.3.2 ADLAR = 1
    • 19.10.4 ADCSRB - ADC Control and Status Register B
    • 19.10.5 DIDR0 - Digital Input Disable Register 0
    • 19.10.6 DIDR1 - Digital Input Disable Register 1
• 20. debugWIRE On-chip Debug System
  • 20.1 Features
  • 20.2 Overview
  • 20.3 Physical Interface
  • 20.4 Software Break Points
  • 20.5 Limitations of debugWIRE
  • 20.6 Register Description
    • 20.6.1 DWDR - debugWire Data Register
• 21. Self-Programming the Flash
  • 21.0.1 Performing Page Erase by SPM
  • 21.0.2 Filling the Temporary Buffer (Page Loading)
  • 21.0.3 Performing a Page Write
  • 21.1 Addressing the Flash During Self-Programming
    • 21.1.1 EEPROM Write Prevents Writing to SPMCSR
    • 21.1.2 Reading the Fuse and Lock Bits from Software
    • 21.1.3 Preventing Flash Corruption
    • 21.1.4 Programming Time for Flash when Using SPM
  • 21.2 Register Description
    • 21.2.1 SPMCSR - Store Program Memory Control and Status Register
• 22. Memory Programming
  • 22.1 Program And Data Memory Lock Bits
  • 22.2 Fuse Bytes
    • 22.2.1 Latching of Fuses
  • 22.3 Signature Bytes
  • 22.4 Calibration Byte
  • 22.5 Page Size
  • 22.6 Parallel Programming Parameters, Pin Mapping, and Commands
    • 22.6.1 Signal Names
  • 22.7 Parallel Programming
    • 22.7.1 Enter Programming Mode
    • 22.7.2 Considerations for Efficient Programming
    • 22.7.3 Chip Erase
    • 22.7.4 Programming the Flash
    • 22.7.5 Programming the EEPROM
    • 22.7.6 Reading the Flash
    • 22.7.7 Reading the EEPROM
    • 22.7.8 Programming the Fuse Low Bits
    • 22.7.9 Programming the Fuse High Bits
    • 22.7.10 Programming the Extended Fuse Bits
    • 22.7.11 Programming the Lock Bits
    • 22.7.12 Reading the Fuse and Lock Bits
    • 22.7.13 Reading the Signature Bytes
    • 22.7.14 Reading the Calibration Byte
  • 22.8 Serial Downloading
    • 22.8.1 Serial Programming Algorithm
    • 22.8.2 Serial Programming Instruction set
• 23. Electrical Characteristics
  • 23.1 Absolute Maximum Ratings*
  • 23.2 DC Characteristics
  • 23.3 Speed Grades
  • 23.4 Clock Characteristics
    • 23.4.1 Calibrated Internal RC Oscillator Accuracy
    • 23.4.2 External Clock Drive Waveforms
    • 23.4.3 External Clock Drive
  • 23.5 System and Reset Characteristics
  • 23.6 ADC Characteristics - Preliminary Data
  • 23.7 Parallel Programming Characteristics
  • 23.8 Serial Programming Characteristics
• 24. Typical Characteristics
  • 24.1 Active Supply Current
  • 24.2 Idle Supply Current
  • 24.3 Supply Current of I/O modules
    • Example
  • 24.4 Power-down Supply Current
  • 24.5 Pin Pull-up
  • 24.6 Pin Driver Strength
  • 24.7 Pin Threshold and Hysteresis
  • 24.8 BOD Threshold and Analog Comparator Offset
  • 24.9 Internal Oscillator Speed
  • 24.10 Current Consumption of Peripheral Units
  • 24.11 Current Consumption in Reset and Reset Pulsewidth
• 25. Register Summary
• 26. Instruction Set Summary
• 27. Ordering Information
  • 27.1 ATtiny261
  • 27.2 ATtiny461
  • 27.3 ATtiny861
• 28. Packaging Information
  • 28.1 32M1-A
  • 28.2 20P3
  • 28.3 20S2
• 29. Errata
  • 29.1 Errata ATtiny261
    • 29.1.1 Rev A
  • 29.2 Errata ATtiny461
    • 29.2.1 Rev B
    • 29.2.2 Rev A
  • 29.3 Errata ATtiny861
    • 29.3.1 Rev B
    • 29.3.2 Rev A
• 30. Datasheet Revision History
  • 30.1 Rev. 2588A - 11/06
  • 30.2 Rev. 2588A - 10/06
• Table of Contents