Document Outline

• DESCRIPTION
  • Standards
• FEATURE HIGHLIGHTS
  • General
  • Line Interface
  • Clock Synthesizer
  • Jitter Attenuator
  • Framer/Formatter
  • System Interface
  • HDLC Controllers
  • Test and Diagnostics
  • Extended System Information Bus
  • Control Port
• BLOCK DIAGRAM
• DS21455/DS21458 DELTA
  • Package
  • Controller Interface
  • ESIB Function
  • Framer/LIU Interim Signals
• PIN FUNCTION DESCRIPTION
  • Transmit Side Pins
  • Receive Side Pins
  • Parallel Control Port Pins
  • Extended System Information Bus
  • JTAG Test Access Port Pins
  • Line Interface Pins
  • Supply Pins
  • Pin Descriptions
  • Packages
• PARALLEL PORT
  • Register Map
• SPECIAL PER-CHANNEL REGISTER OPERATION
• PROGRAMMING MODEL
  • Power-Up Sequence
    • Master Mode Register
  • Interrupt Handling
  • Status Registers
  • Information Registers
  • Interrupt Information Registers
• CLOCK MAP
• T1 FRAMER/FORMATTER CONTROL REGISTERS
  • T1 Control Registers
  • T1 Transmit Transparency
  • AIS-CI and RAI-CI Generation and Detection
  • T1 Receive-Side Digital-Milliwatt Code Generation
  • T1 Information Register
• E1 FRAMER/FORMATTER CONTROL REGISTERS
  • E1 Control Registers
  • Automatic Alarm Generation
    • Auto AIS
    • Auto RAI
    • Auto E-Bit
    • G.706 CRC-4 Interworking
  • E1 Information Registers
• COMMON CONTROL AND STATUS REGISTERS
• I/O PIN CONFIGURATION OPTIONS
• LOOPBACK CONFIGURATIONS
  • Per-Channel Payload Loopback
• ERROR COUNT REGISTERS
  • Line Code Violation Count Register (LCVCR)
    • T1 Operation
    • E1 Operation
  • Path Code Violation Count Register (PCVCR)
    • T1 Operation
      • WHAT IS COUNTED IN THE PCVCRs
    • E1 Operation
  • Frames Out Of Sync Count Register (FOSCR)
    • T1 Operation
    • E1 Operation
  • E-Bit Counter Register (EBCR)
• DS0 MONITORING FUNCTION
  • Transmit DS0 Monitor Registers
  • Receive DS0 Monitor Registers
• SIGNALING OPERATION
  • Receive Signaling
    • Processor-Based Receive Signaling
      • Change Of State
    • Hardware-Based Receive Signaling
      • Receive-Signaling Reinsertion at RSER
      • Force Receive Signaling All Ones
      • Receive-Signaling Freeze
  • Transmit Signaling
    • Processor-Based Transmit Signaling
      • T1 Mode
      • E1 Mode
    • Software Signaling Insertion Enable Registers, E1 CAS Mode
    • Software Signaling Insertion Enable Registers, T1 Mode
• PER-CHANNEL IDLE CODE GENERATION
  • Idle Code Programming Examples
• CHANNEL BLOCKING REGISTERS
• ELASTIC STORES OPERATION
  • Receive Side
    • T1 Mode
    • E1 Mode
  • Transmit Side
    • T1 Mode
    • E1 Mode
  • Elastic Stores Initialization
  • Minimum-Delay Mode
• G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)
• T1 BIT ORIENTED CODE (BOC) CONTROLLER
  • Transmit BOC
  • Receive BOC
• ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)
  • Hardware Scheme (Method 1)
  • Internal Register Scheme Based On Double-Frame (Method 2)
  • Internal Register Scheme Based On CRC-4 Multiframe (Method 3)
• HDLC CONTROLLERS
  • Basic Operation Details
  • HDLC Configuration
    • FIFO Control
  • HDLC Mapping
    • Receive
    • Transmit
    • FIFO Information
    • Receive Packet Bytes Available
    • HDLC FIFOS
  • Receive HDLC Code Example
  • Legacy FDL Support (T1 Mode)
    • Receive Section
    • Transmit Section
  • D4/SLC-96 Operation
• LINE INTERFACE UNIT (LIU)
  • LIU Operation
  • LIU Receiver
    • Receive Level Indicator
    • Receive G.703 Section 10 Synchronization Signal
    • Monitor Mode
  • LIU Transmitter
    • Transmit Short-Circuit Detector/Limiter
    • Transmit Open-Circuit Detector
    • Transmit BPV Error Insertion
    • Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
  • MCLK Prescaler
  • Jitter Attenuator
  • CMI (Code Mark Inversion) Option
  • LIU Control Registers
  • Recommended Circuits
  • Component Specifications
• PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION
• BERT FUNCTION
  • BERT Register Description
  • BERT Repetitive Pattern Set
  • BERT Bit Counter
  • BERT Error Counter
• PAYLOAD ERROR INSERTION FUNCTION
  • Number of Error Registers
    • Number of Errors Left Register
• INTERLEAVED PCM BUS OPERATION
  • Channel Interleave Mode
  • Frame Interleave Mode
• EXTENDED SYSTEM INFORMATION BUS (ESIB)
• PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER
• FRACTIONAL T1/E1 SUPPORT
• USER-PROGRAMMABLE OUTPUT PINS
• TRANSMIT FLOW DIAGRAMS
• JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT
  • Instruction Register
  • Test Registers
  • Boundary Scan Register
  • Bypass Register
  • Identification Register
• FUNCTIONAL TIMING DIAGRAMS
  • T1 Mode
  • E1 Mode
• OPERATING PARAMETERS
• AC TIMING PARAMETERS AND DIAGRAMS
  • Multiplexed Bus AC Characteristics
  • Nonmultiplexed Bus AC Characteristics
  • Receive Side AC Characteristics
  • Transmit AC Characteristics
• PACKAGE INFORMATION