Document Outline

• Introduction
  • Applications of the ERTEC 200
  • Features of the ERTEC 200
  • Structure of the ERTEC 200
  • ERTEC 200 Package
  • Signal Function Description
    • GPIO 0 to 31 and Alternative Functions
    • JTAG and Debug
    • Trace Port
    • Clock and Reset
    • Test Pins
    • EMIF (External Memory Interface)
    • LBU, MII Interface or ETM Trace Interface
    • Ethernet PHY1 and PHY2
    • Power Supply
• UARM946E-S Processor
  • Structure of ARM946E-S
  • Description of ARM946E-S
  • Operating Frequency of ARM946E-S
  • Cache Structure of ARM946E-S
  • Tightly Coupled Memory (TCM)
  • Memory Protection Unit (MPU)
  • Bus Interface of ARM946E-S
  • ARM946E-S Embedded Trace Macrocell (ETM9)
  • ARM Interrupt Controller (ICU)
    • Prioritization of Interrupts
    • Trigger Modes
    • Masking the Interrupt Inputs
    • Software Interrupts for IRQ
    • Nested Interrupt Structure
    • EOI End-Of-Interrupt
    • IRQ Interrupt Sources
    • FIQ Interrupt Sources
    • IRQ Interrupts as FIQ Interrupt Sources
    • Interrupt Control Register
    • ICU Register Description
  • ARM946E-S Register
• Bus System of the ERTEC 200
  • “Multilayer AHB” Communication Bus
    • AHB Arbiter
    • AHB Master-Slave Coupling
  • APB I/O Bus
• I/O on APB bus
  • BOOT ROM
    • Booting from External ROM
    • Booting via SPI
    • Booting via UART
    • Booting via LBU
    • Memory Swapping
  • General Purpose I/O (GPIO)
    • Address Assignment of GPIO Registers
    • GPIO Register Description
  • Timer 0/1/2
    • Timer 0 and Timer 1
      • Timer 0/1 Interrupts
      • Timer 0/1 Prescaler
      • Cascading of Timers 0/1
    • Timer 2
    • Address Assignment of Timer Registers
    • Timer Register Description
  • F-Timer Function
    • Address Assignment of F-Timer Registers
    • F-Timer Register Description
  • Watchdog Timers
    • Watchdog Timer 0
    • Watchdog Timer 1
    • Watchdog Interrupt
    • WDOUT0_N
    • WDOUT1_N
    • Watchdog Registers
    • Address Assignment of Watchdog Registers
    • Watchdog Register Description
  • UART Interface
    • Address Assignment of UART Registers
    • UART Register Description
  • Synchronous Interface SPI
    • Address Assignment of SPI Register
    • SPI Register Description
  • System control register
    • Address Assignment of System Control Registers
    • System Control Register Description
• General Hardware Functions
  • Clock Generation and Clock Supply
    • Clock Supply in ERTEC 200
    • JTAG Clock Supply
    • Clock Supply for PHYs and Ethernet MACs
  • Reset Logic of the ERTEC 200
    • PowerOn reset
    • Hardware Reset
    • Watchdog Reset
    • Software reset
    • IRT Switch Reset
  • Address Space and Timeout Monitoring
    • AHB Bus Monitoring
    • APB Bus Monitoring
    • EMIF Monitoring
  • Configuration Options on the ERTEC 200
• External Memory Interface (EMIF)
  • Address Assignment of EMIF Registers
  • EMIF Register Description
• Local Bus Unit (LBU).
  • Page Range Setting
  • Page Offset Setting
  • LBU Address Mapping
  • Page Control Setting
  • Host Access to the ERTEC200
    • LBU Read from ERTEC 200 with separate Read/Write line (LBU_R
    • LBU Write to ERTEC 200 with separate Read/Write line (LBU_RD
    • LBU Read from ERTEC 200 with common Read/Write line (LBU_RDY
    • LBU Write to ERTEC 200 with common Read/Write line (LBU_RDY_
  • Host Interrupt Handling:
  • Address Assignment of LBU Registers
  • LBU Register Description
• DMA-Controller
  • DMA Register Address Assignment
  • Description of DMA Registers
• Multiport Ethernet PHY
• Memory Description
  • Memory Partitioning of the ERTEC 200
  • Detailed Memory Description
• Test and Debugging
  • ETM9 Embedded Trace Macrocell
    • Trace Modes
    • Features of the ETM9 Module
    • ETM9 Registers
  • Trace Interface
  • JTAG Interface
  • Debugging via UART
• Miscellaneous
  • Acronyms/Glossary:
  • References: