Document Outline

• 1. Any-Frequency Precision Clock Product Family Overview
• 2. Wideband Devices
  • 2.1. Narrowband vs. Wideband Overview
• 3. Any-Frequency Clock Family Members
  • 3.1. Si5316
  • 3.2. Si5319
  • 3.3. Si5322
  • 3.4. Si5323
  • 3.5. Si5324
  • 3.6. Si5325
  • 3.7. Si5326
  • 3.8. Si5327
  • 3.9. Si5328
  • 3.10. Si5365
  • 3.11. Si5366
  • 3.12. Si5367
  • 3.13. Si5368
  • 3.14. Si5369
  • 3.15. Si5374/75/76 Compared to Si5324/19/26
  • 3.16. Si5374
  • 3.17. Si5375
  • 3.18. Si5376
• 4. DSPLL (All Devices)
  • 4.1. Clock Multiplication
  • 4.2. PLL Performance
    • 4.2.1. Jitter Generation
    • 4.2.2. Jitter Transfer
    • 4.2.3. Jitter Tolerance
• 5. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
  • 5.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)
    • 5.1.1. Clock Multiplication (Si5316)
    • 5.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366)
    • 5.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366)
    • 5.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)
    • 5.1.5. Jitter Tolerance (Si5316, Si5323, Si5366)
    • 5.1.6. Narrowband Performance (Si5316, Si5323, Si5366)
    • 5.1.7. Input-to-Output Skew (Si5316, Si5323, Si5366)
    • 5.1.8. Wideband Performance (Si5322 and Si5365)
    • 5.1.9. Lock Detect (Si5322 and Si5365)
    • 5.1.10. Input-to-Output Skew (Si5322 and Si5365)
  • 5.2. PLL Self-Calibration
    • 5.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5322, Si5323, Si5365, Si5366)
    • 5.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)
    • 5.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366)
  • 5.3. Pin Control Input Clock Control
    • 5.3.1. Manual Clock Selection
    • 5.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)
    • 5.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366)
  • 5.4. Digital Hold/VCO Freeze
    • 5.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366)
    • 5.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366)
    • 5.4.3. Wideband VCO Freeze (Si5322, Si5365)
  • 5.5. Frame Synchronization (Si5366)
  • 5.6. Output Phase Adjust (Si5323, Si5366)
    • 5.6.1. FSYNC Realignment (Si5366)
    • 5.6.2. Including FSYNC Inputs in Clock Selection (Si5366)
    • 5.6.3. FS_OUT Polarity and Pulse Width Control (Si5366)
    • 5.6.4. Using FS_OUT as a Fifth Output Clock (Si5366)
    • 5.6.5. Disabling FS_OUT (Si5366)
  • 5.7. Output Clock Drivers
    • 5.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)
  • 5.8. PLL Bypass Mode
  • 5.9. Alarms
    • 5.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366)
    • 5.9.2. FOS Alarms (Si5365 and Si5366)
    • 5.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L)
    • 5.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323)
    • 5.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366)
  • 5.10. Device Reset
  • 5.11. DSPLLsim Configuration Software
• 6. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)
  • 6.1. Clock Multiplication
    • 6.1.1. Jitter Tolerance (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.1.2. Wideband Parts (Si5325, Si5367)
    • 6.1.3. Narrowband Parts (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375, and Si5376)
    • 6.1.5. Lock Detect (Si5319, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
  • 6.2. PLL Self-Calibration
    • 6.2.1. Initiating Internal Self-Calibration
    • 6.2.2. Input Clock Stability during Internal Self-Calibration
    • 6.2.3. Self-Calibration Caused by Changes in Input Frequency
    • 6.2.4. Narrowband Input-to-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.2.5. Clock Output Behavior Before and During ICAL (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
  • 6.3. Input Clock Configurations (Si5367 and Si5368)
  • 6.4. Input Clock Control
    • 6.4.1. Manual Clock Selection (Si5324, Si5325, Si5326, Si5328, Si5367, Si5368, Si5369, Si5374, and Si5376)
    • 6.4.2. Automatic Clock Selection (Si5324, Si5325, Si5326, Si5328, Si5367, Si5368, Si5369, Si5374, and Si5376)
    • 6.4.3. Hitless Switching with Phase Build-Out (Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)
  • 6.5. Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376 Free Run Mode
    • 6.5.1. Free Run Mode Programming Procedure
    • 6.5.2. Clock Control Logic in Free Run Mode
    • 6.5.3. Free Run Reference Frequency Constraints
    • 6.5.4. Free Run Reference Frequency Constraints
  • 6.6. Digital Hold
    • 6.6.1. Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5328, Si5368, Si5369, Si5374, Si5376)
    • 6.6.2. History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5328, Si5369, Si5374)
    • 6.6.3. Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)
    • 6.6.4. VCO Freeze (Si5319, Si5325, Si5367, Si5375)
    • 6.6.5. Digital Hold versus VCO Freeze
  • 6.7. Output Phase Adjust (Si5326, Si5368)
    • 6.7.1. Coarse Skew Control (Si5326, Si5368)
    • 6.7.2. Fine Skew Control (Si5326, Si5368)
    • 6.7.3. Independent Skew (Si5324, Si5326, Si5328, Si5368, Si5369, Si5374, and Si5376)
    • 6.7.4. Output-to-output Skew (Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, and Si5376)
    • 6.7.5. Input-to-Output Skew (All Devices)
  • 6.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)
    • 6.8.1. FSYNC Realignment (Si5368)
    • 6.8.2. FSYNC Skew Control (Si5368)
    • 6.8.3. Including FSYNC Inputs in Clock Selection (Si5368)
    • 6.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)
    • 6.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)
  • 6.9. Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, Si5376)
    • 6.9.1. Disabling CKOUTn
    • 6.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)
  • 6.10. PLL Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)
  • 6.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.11.1. Loss-of-Signal Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.11.2. FOS Algorithm (Si5324, Si5325, Si5326, Si5328, Si5368, Si5369, Si5374, and Si5376)
    • 6.11.3. C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5374, Si5375, and Si5376)
    • 6.11.4. LOS (Si5319, Si5375)
    • 6.11.5. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368, Si5369 [CK_CONFIG_REG = 0])
    • 6.11.6. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1])
    • 6.11.7. LOS Algorithm for Reference Clock Input (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
    • 6.11.9. Device Interrupts
  • 6.12. Device Reset
  • 6.13. I2C Serial Microprocessor Interface
  • 6.14. Serial Microprocessor Interface (SPI)
    • 6.14.1. Default Device Configuration
  • 6.15. Register Descriptions
  • 6.16. DSPLLsim Configuration Software
• 7. High-Speed I/O
  • 7.1. Input Clock Buffers
  • 7.2. Output Clock Drivers
    • 7.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)
    • 7.2.2. Typical Output Circuits
    • 7.2.3. Typical Clock Output Scope Shots
  • 7.3. Typical Scope Shots for SFOUT Options
  • 7.4. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5328, Si5366, Si5368, Si5369, Si5374, Si5375, and Si5376)
  • 7.5. Three-Level (3L) Input Pins (No External Resistors)
  • 7.6. Three-Level (3L) Input Pins (With External Resistors)
• 8. Power Supply
• 9. Packages and Ordering Guide
• Appendix A—Narrowband References
• Appendix B—Frequency Plans and Typical Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375, and Si5376)
• Appendix C—Typical Phase Noise Plots
• Appendix D—Alarm Structure
• Appendix E—Internal Pullup, Pulldown by Pin
• Appendix F—Typical Performance: Bypass Mode, PSRR, Crosstalk, Output Format Jitter
• Appendix G—Near Integer Ratios
• Appendix H—Jitter Attenuation and Loop BW
• Appendix I—Response to a Frequency Step Function
• Appendix J—Si5374, Si5375, Si5376 PCB Layout Recommendations
• Appendix K—Si5374, Si5375, and Si5376 Crosstalk
• Appendix L—Jitter Transfer and Peaking
• Document Change List
• Contact Information