Document Outline

• Table of Contents
• Preface
• 1 Overview
  • 1.1 Scope of the Standard
    • 1.1.1 Rules and Guidelines
  • 1.2 Requirements of the Standard
  • 1.3 Goals of the Standard
  • 1.4 Intentional Omissions
  • 1.5 System Architecture
    • 1.5.1 Frameworks
    • 1.5.2 Algorithms
    • 1.5.3 Core Run-Time Support
• 2 General Programming Guidelines
  • 2.1 Use of C Language
  • 2.2 Threads and Reentrancy
    • 2.2.1 Threads
    • 2.2.2 Preemptive vs. Non-Preemptive Multitasking
    • 2.2.3 Reentrancy
    • 2.2.4 Example
  • 2.3 Data Memory
    • 2.3.1 Memory Spaces
    • 2.3.2 Scratch versus Persistent
    • 2.3.3 Algorithm versus Application
  • 2.4 Program Memory
  • 2.5 ROM-ability
  • 2.6 Use of Peripherals
• 3 Algorithm Component Model
  • 3.1 Interfaces and Modules
    • 3.1.1 External Identifiers
    • 3.1.2 Naming Conventions
    • 3.1.3 Module Initialization and Finalization
    • 3.1.4 Module Instance Objects
    • 3.1.5 Design-Time Object Creation
    • 3.1.6 Run-Time Object Creation and Deletion
    • 3.1.7 Module Configuration
    • 3.1.8 Example Module
    • 3.1.9 Multiple Interface Support
    • 3.1.10 Interface Inheritance
    • 3.1.11 Summary
  • 3.2 Algorithms
  • 3.3 Packaging
    • 3.3.1 Object Code
    • 3.3.2 Header Files
    • 3.3.3 Debug Verses Release
• 4 Algorithm Performance Characterization
  • 4.1 Data Memory
    • 4.1.1 Heap Memory
    • 4.1.2 Stack Memory
    • 4.1.3 Static Local and Global Data Memory
  • 4.2 Program Memory
  • 4.3 Interrupt Latency
  • 4.4 Execution Time
    • 4.4.1 MIPS Is Not Enough
    • 4.4.2 Execution Time Model
• 5 DSP-Specific Guidelines
  • 5.1 CPU Register Types
  • 5.2 Use of Floating Point
  • 5.3 TMS320C6xxx Rules and Guidelines
    • 5.3.1 Endian Byte Ordering
    • 5.3.2 Data Models
    • 5.3.3 Program Model
    • 5.3.4 Register Conventions
    • 5.3.5 Status Register
    • 5.3.6 Interrupt Latency
  • 5.4 TMS320C54xx Rules and Guidelines
    • 5.4.1 Data Models
    • 5.4.2 Program Models
    • 5.4.3 Register Conventions
    • 5.4.4 Status Registers
    • 5.4.5 Interrupt Latency
  • 5.5 TMS320C55x Rules and Guidelines
    • 5.5.1 Stack Architecture
    • 5.5.2 Data Models
    • 5.5.3 Program Models
    • 5.5.4 Relocatability
    • 5.5.5 Register Conventions
    • 5.5.6 Status Bits
  • 5.6 TMS320C24xx Guidelines
    • 5.6.1 General
    • 5.6.2 Data Models
    • 5.6.3 Program Models
    • 5.6.4 Register Conventions
    • 5.6.5 Status Registers
    • 5.6.6 Interrupt Latency
  • 5.7 TMS320C28x Rules and Guidelines
    • 5.7.1 Data Models
    • 5.7.2 Program Models
    • 5.7.3 Register Conventions
    • 5.7.4 Status Registers
    • 5.7.5 Interrupt Latency
• 6 Use of the DMA Resource
  • 6.1 Overview
  • 6.2 Algorithm and Framework
  • 6.3 Requirements for the Use of the DMA Resource
  • 6.4 Logical Channel
  • 6.5 Data Transfer Properties
  • 6.6 Data Transfer Synchronization
  • 6.7 Abstract Interface
  • 6.8 Resource Characterization
  • 6.9 Runtime APIs
  • 6.10 Strong Ordering of DMA Transfer Requests
  • 6.11 Submitting DMA Transfer Requests
  • 6.12 Device Independent DMA Optimization Guideline
  • 6.13 C6xxx Specific DMA Rules and Guidelines
    • 6.13.1 Cache Coherency Issues for Algorithm Producers
  • 6.14 C55x Specific DMA Rules and Guidelines
    • 6.14.1 Supporting Packed/Burst Mode DMA Transfers
    • 6.14.2 Minimizing Logical Channel Reconfiguration Overhead
    • 6.14.3  Addressing Automatic Endianism Conversion Issues
  • 6.15 Inter-Algorithm Synchronization
    • 6.15.1  Non-Preemptive System
    • 6.15.3 Preemptive System
• A Rules and Guidelines
  • A.1 General Rules
  • A.2 Performance Characterization Rules
  • A.3 DMA Rules
  • A.4 General Guidelines
  • A.5 DMA Guidelines
• B Core Run-Time APIs
  • B.1 TI C-Language Run-Time Support Library
  • B.2 DSP/BIOS Run-time Support Library
• C Bibliography
  • C.1 Books
  • C.2 URLS
• D Glossary
  • D.1 Glossary of Terms