Document Outline

• SPRS293A - TMS320C6712D
• features
• Table of Contents
• REVISION HISTORY
• GDP and ZDP BGA package (bottom view)
• description
• device characteristics
• device compatibility
• functional block and CPU (DSP core) diagram
• CPU (DSP core) description
• memory map summary
• peripheral register descriptions
• signal groups description
• DEVICE CONFIGURATIONS
  • device configurations at device reset
  • DEVCFG register description
• TERMINAL FUNCTIONS
  • Terminal Functions
• development support
  • Software Development Tools:
  • Hardware Development Tools:
• device support
  • device and development-support tool nomenclature
    • TMX
    • TMP
    • TMS
    • TMDX
    • TMDS
  • documentation support
• CPU CSR register description
• cache configuration (CCFG) register description
• interrupt sources and interrupt selector
• EDMA module and EDMA selector
  • ESEL0 Register (0x01A0 FF00)
  • ESEL1 Register (0x01A0 FF04)
  • ESEL3 Register (0x01A0 FF0C)
• PLL and PLL controller
  • PLLCSR Register (0x01B7 C100)
  • PLLM Register (0x01B7 C110)
  • Table 29. PLL Multiplier Control Register (PLLM)
  • PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers
  • OSCDIV1 Register (0x01B7 C124)
• general-purpose input/output (GPIO)
• power-down mode logic
  • triggering, wake-up, and effects
• power-supply sequencing
  • system-level design considerations
  • power-supply design considerations
• power-supply decoupling
• IEEE 1149.1 JTAG compatibility statement
• EMIF device speed
• EMIF big endian mode correctness
• bootmode
• reset
• absolute maximum ratings over operating case temperature range (unless otherwise noted)†
• recommended operating conditions
• electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)
• PARAMETER MEASUREMENT INFORMATION
  • signal transition levels
  • AC transient rise/fall time specifications
  • timing parameters and board routing analysis
• INPUT AND OUTPUT CLOCKS
  • timing requirements for CLKIN†‡§ (see Figure 21)
  • switching characteristics over recommended operating conditions for CLKOUT2‡§ (see Figure 22)
  • switching characteristics over recommended operating conditions for CLKOUT3†‡ ( see Figure 23)
  • timing requirements for ECLKIN§ (see Figure 24)
  • switching characteristics over recommended operating conditions for ECLKOUT†‡§ (see Figure 25)
• ASYNCHRONOUS MEMORY TIMING
  • timing requirements for asynchronous memory cycles†‡ (see Figure 26-Figure 27)
  • switching characteristics over recommended operating conditions for asynchronous memory cycles‡§¶ (see Figure 26-Figure 27)
• SYNCHRONOUS-BURST MEMORY TIMING
  • timing requirements for synchronous-burst SRAM cycles† (see Figure 28)
  • switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ ( see Figure 28 and Figure 29)
• SYNCHRONOUS DRAM TIMING
  • timing requirements for synchronous DRAM cycles† (see Figure 30)
  • switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ ( see Figure 30- Figure 36)
• HOLD\/HOLDA\ TIMING
  • timing requirements for the HOLD\/HOLDA\ cycles† (see Figure 37)
  • switching characteristics over recommended operating conditions for the HOLD\/HOLDA\ cycles†‡ ( see Figure 37)
• BUSREQ TIMING
  • switching characteristics over recommended operating conditions for the BUSREQ cycles ( see Figure 38)
• RESET TIMING
  • timing requirements for reset†‡ (see Figure 39)
  • switching characteristics over recommended operating conditions during reset¶ (see Figure 39)
• EXTERNAL INTERRUPT TIMING
  • timing requirements for external interrupts† (see Figure 40)
• MULTICHANNEL BUFFERED SERIAL PORT TIMING
  • timing requirements for McBSP†‡ ( see Figure 41)
  • switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 41)
  • timing requirements for FSR when GSYNC = 1 (see Figure 42)
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 43)
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 43)
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 44)
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 44)
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 45)
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 45)
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 46)
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 46)
• TIMER TIMING
  • timing requirements for timer inputs† (see Figure 47)
  • switching characteristics over recommended operating conditions for timer outputs† ( see Figure 47)
• GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
  • timing requirements for GPIO inputs†‡ (see Figure 48)
  • switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 48)
• JTAG TEST-PORT TIMING
  • timing requirements for JTAG test port (see Figure 49)
  • switching characteristics over recommended operating conditions for JTAG test port ( see Figure 49)
• MECHANICAL DATA
  • package thermal resistance characteristics
  • thermal resistance characteristics (S-PBGA package) for GDP
  • thermal resistance characteristics (S-PBGA package) for ZDP
  • packaging information