Document Outline

• Title Page - SPRU733
• IMPORTANT NOTICE
• Read This First
  • About This Manual
  • Notational Conventions
  • Related Documentation From Texas Instruments
  • Trademarks
• Contents
• Figures
• Tables
• Examples
• Chapter 1: Introduction
  • 1.1 TMS320 DSP Family Overview
  • 1.2 TMS320C6000 DSP Family Overview
  • 1.3 TMS320C67x DSP Features and Options
  • 1.4 TMS320C67x DSP Architecture
    • 1.4.1 Central Processing Unit (CPU)
    • 1.4.2 Internal Memory
    • 1.4.3 Memory and Peripheral Options
• Chapter 2: CPU Data Paths and Control
  • 2.1 Introduction
  • 2.2 General-Purpose Register Files
  • 2.3 Functional Units
  • 2.4 Register File Cross Paths
  • 2.5 Memory, Load, and Store Paths
  • 2.6 Data Address Paths
  • 2.7 Control Register File
    • 2.7.1 Register Addresses for Accessing the Control Registers
    • 2.7.2 Pipeline/Timing of Control Register Accesses
    • 2.7.3 Addressing Mode Register (AMR)
    • 2.7.4 Control Status Register (CSR)
    • 2.7.5 Interrupt Clear Register (ICR)
    • 2.7.6 Interrupt Enable Register (IER)
    • 2.7.7 Interrupt Flag Register (IFR)
    • 2.7.8 Interrupt Return Pointer Register (IRP)
    • 2.7.9 Interrupt Set Register (ISR)
    • 2.7.10 Interrupt Service Table Pointer Register (ISTP)
    • 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
    • 2.7.12 E1 Phase Program Counter (PCE1)
  • 2.8 Control Register File Extensions
    • 2.8.1 Floating-Point Adder Configuration Register (FADCR)
    • 2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR)
    • 2.8.3 Floating-Point Multiplier Configuration Register (FMCR)
• Chapter 3: Instruction Set
  • 3.1 Instruction Operation and Execution Notations
  • 3.2 Instruction Syntax and Opcode Notations
  • 3.3 Overview of IEEE Standard Single- and Double-Precision Formats
  • 3.4 Delay Slots
  • 3.5 Parallel Operations
    • 3.5.1 Example Parallel Code
    • 3.5.2 Branching Into the Middle of an Execute Packet
  • 3.6 Conditional Operations
  • 3.7 Resource Constraints
    • 3.7.1 Constraints on Instructions Using the Same Functional Unit
    • 3.7.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle
    • 3.7.3 Constraints on Cross Paths (1X and 2X)
    • 3.7.4 Constraints on Loads and Stores
    • 3.7.5 Constraints on Long (40-Bit) Data
    • 3.7.6 Constraints on Register Reads
    • 3.7.7 Constraints on Register Writes
    • 3.7.8 Constraints on Floating-Point Instructions
  • 3.8 Addressing Modes
    • 3.8.1 Linear Addressing Mode
      • 3.8.1.1 LD and ST Instructions
      • 3.8.1.2 ADDA and SUBA Instructions
    • 3.8.2 Circular Addressing Mode
      • 3.8.2.1 LD and ST Instructions
      • 3.8.2.2 ADDA and SUBA Instructions
    • 3.8.3 Syntax for Load/Store Address Generation
  • 3.9 Instruction Compatibility
  • 3.10 Instruction Descriptions
    • Example
    • ABS
    • ABSDP
    • ABSSP
    • ADD
    • ADDAB
    • ADDAD
    • ADDAH
    • ADDAW
    • ADDDP
    • ADDK
    • ADDSP
    • ADDU
    • ADD2
    • AND
    • B displacement
    • B register
    • B IRP
    • B NRP
    • CLR
    • CMPEQ
    • CMPEQDP
    • CMPEQSP
    • CMPGT
    • CMPGT
    • CMPGTDP
    • CMPGTSP
    • CMPGTU
    • CMPLT
    • CMPLTDP
    • CMPLTSP
    • CMPLTU
    • DPINT
    • DPSP
    • DPTRUNC
    • EXT
    • EXTU
    • IDLE
    • INTDP
    • INTDPU
    • INTSP
    • INTSPU
    • LDB(U)
    • LDB(U)
    • LDDW
    • LDH(U)
    • LDH(U)
    • LDW
    • LDW
    • LMBD
    • MPY
    • MPYDP
    • MPYH
    • MPYHL
    • MPYHLU
    • MPYHSLU
    • MPYHSU
    • MPYHU
    • MPYHULS
    • MPYHUS
    • MPYI
    • MPYID
    • MPYLH
    • MPYLHU
    • MPYLSHU
    • MPYLUHS
    • MPYSP
    • MPYSPDP
    • MPYSP2DP
    • MPYSU
    • MPYU
    • MPYUS
    • MV
    • MVC
    • MVK
    • MVKH/MVKLH
    • MVKL
    • NEG
    • NOP
    • NORM
    • NOT
    • OR
    • RCPDP
    • RCPSP
    • RSQRDP
    • RSQRSP
    • SADD
    • SAT
    • SET
    • SHL
    • SHR
    • SHRU
    • SMPY
    • SMPYH
    • SMPYHL
    • SMPYLH
    • SPDP
    • SPINT
    • SPTRUNC
    • SSHL
    • SSUB
    • STB
    • STB
    • STH
    • STH
    • STW
    • STW
    • SUB
    • SUBAB
    • SUBAH
    • SUBAW
    • SUBC
    • SUBDP
    • SUBSP
    • SUBU
    • SUB2
    • XOR
    • ZERO
• Chapter4: Pipeline
  • 4.1 Pipeline Operation Overview
    • 4.1.1 Fetch
    • 4.1.2 Decode
    • 4.1.3 Execute
    • 4.1.4 Pipeline Operation Summary
  • 4.2 Pipeline Execution of Instruction Types
    • 4.2.1 Single-Cycle Instructions
    • 4.2.2 16 x 16-Bit Multiply Instructions
    • 4.2.3 Store Instructions
    • 4.2.4 Load Instructions
    • 4.2.5 Branch Instructions
    • 4.2.6 Two-Cycle DP Instructions
    • 4.2.7 Four-Cycle Instructions
    • 4.2.8 INTDP Instruction
    • 4.2.9 DP Compare Instructions
    • 4.2.10 ADDDP/SUBDP Instructions
    • 4.2.11 MPYI Instruction
    • 4.2.12 MPYID Instruction
    • 4.2.13 MPYDP Instruction
    • 4.2.14 MPYSPDP Instruction
    • 4.2.15 MPYSP2DP Instruction
  • 4.3 Functional Unit Constraints
    • 4.3.1 .S-Unit Constraints
    • 4.3.2 .M-Unit Constraints
    • 4.3.3 .L-Unit Constraints
    • 4.3.4 .D-Unit Instruction Constraints
  • 4.4 Performance Considerations
    • 4.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet
    • 4.4.2 Multicycle NOPs
    • 4.4.3 Memory Considerations
      • 4.4.3.1 Memory Stalls
      • 4.4.3.2 Memory Bank Hits
• Chapter 5: Interrupts
  • 5.1 Overview
    • 5.1.1 Types of Interrupts and Signals Used
      • 5.1.1.1 Reset (RESET)
      • 5.1.1.2 Nonmaskable Interrupt (NMI)
      • 5.1.1.3 Maskable Interrupts (INT4-INT15)
      • 5.1.1.4 Interrupt Acknowledgment (IACK) and Interrupt Number (INUMn)
    • 5.1.2 Interrupt Service Table (IST)
      • 5.1.2.1 Interrupt Service Fetch Packet (ISFP)
      • 5.1.2.2 Interrupt Service Table Pointer (ISTP)
    • 5.1.3 Summary of Interrupt Control Registers
  • 5.2 Globally Enabling and Disabling Interrupts
  • 5.3 Individual Interrupt Control
    • 5.3.1 Enabling and Disabling Interrupts
    • 5.3.2 Status of Interrupts
    • 5.3.3 Setting and Clearing Interrupts
    • 5.3.4 Returning From Interrupt Servicing
      • 5.3.4.1 CPU State After RESET
      • 5.3.4.2 Returning From Nonmaskable Interrupts
      • 5.3.4.3 Returning From Maskable Interrupts
  • 5.4 Interrupt Detection and Processing
    • 5.4.1 Setting the Nonreset Interrupt Flag
    • 5.4.2 Conditions for Processing a Nonreset Interrupt
    • 5.4.3 Actions Taken During Nonreset Interrupt Processing
    • 5.4.4 Setting the RESET Interrupt Flag
    • 5.4.5 Actions Taken During RESET Interrupt Processing
  • 5.5 Performance Considerations
    • 5.5.1 General Performance
    • 5.5.2 Pipeline Interaction
  • 5.6 Programming Considerations
    • 5.6.1 Single Assignment Programming
    • 5.6.2 Nested Interrupts
    • 5.6.3 Manual Interrupt Processing
    • 5.6.4 Traps
• Appendix A: Instruction Compatibility
• Appendix B: Mapping Between Instruction and Functional Unit
• Appendix C: .D Unit Instructions and Opcode Maps
  • C.1 Instructions Executing in the .D Functional Unit
  • C.2 Opcode Map Symbols and Meanings
  • C.3 32-Bit Opcode Maps
• Appendix D: .L Unit Instructions and Opcode Maps
  • D.1 Instructions Executing in the .L Functional Unit
  • D.2 Opcode Map Symbols and Meanings
  • D.3 32-Bit Opcode Maps
• Appendix E: .M Unit Instructions and Opcode Maps
  • E.1 Instructions Executing in the .M Functional Unit
  • E.2 Opcode Map Symbols and Meanings
  • E.3 32-Bit Opcode Maps
• Appendix F: .S Unit Instructions and Opcode Maps
  • F.1 Instructions Executing in the .S Functional Unit
  • F.2 Opcode Map Symbols and Meanings
  • F.3 32-Bit Opcode Maps
• Appendix G: No Unit Specified Instructions and Opcode Maps
  • G.1 Instructions Executing With No Unit Specified
  • G.2 Opcode Map Symbols and Meanings
  • G.3 32-Bit Opcode Maps
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • V
  • X
  • Z