A. write sxcnfg (with enable bits asserted), A. self-refresh and clock-stop, B. self-refresh – Intel PXA26X User Manual

Page 267: C. power-down, D. pwrdnx, E. nop, C. write mdrefr:e1pin (power-down -> pwrdnx), Re-enable the dcache bit if it is disabled

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A. write sxcnfg (with enable bits asserted), A. self-refresh and clock-stop, B. self-refresh | C. power-down, D. pwrdnx, E. nop, C. write mdrefr:e1pin (power-down -> pwrdnx), Re-enable the dcache bit if it is disabled | Intel PXA26X User Manual | Page 267 / 624 A. write sxcnfg (with enable bits asserted), A. self-refresh and clock-stop, B. self-refresh | C. power-down, D. pwrdnx, E. nop, C. write mdrefr:e1pin (power-down -> pwrdnx), Re-enable the dcache bit if it is disabled | Intel PXA26X User Manual | Page 267 / 624
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