2 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) – Intel PXA26X User Manual

Page 434

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2 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) | Intel PXA26X User Manual | Page 434 / 624 2 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) | Intel PXA26X User Manual | Page 434 / 624
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