Table 17-2. rbr bit definitions, 2 transmit holding register (thr), Table 17-3. thr bit definitions – Intel PXA26X User Manual

Table 17-2. rbr bit definitions, 2 transmit holding register (thr), Table 17-3. thr bit definitions | 3 divisor latch registers (dll and dlh), Section 17.5.3, Table 17-2 | Intel PXA26X User Manual | Page 595 / 624