Pru subsystem, Provides two independent, Pru operation is little endian – Texas Instruments MICROPROCESSOR TI SITARA User Manual

Page 26: I/o interface, Bit load/store risc architecture, 4k byte instruction ram (1k instructions) per core, 512 bytes data ram per core

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Pru subsystem, Provides two independent, Pru operation is little endian | I/o interface, Bit load/store risc architecture, 4k byte instruction ram (1k instructions) per core, 512 bytes data ram per core | Texas Instruments MICROPROCESSOR TI SITARA User Manual | Page 26 / 43 Pru subsystem, Provides two independent, Pru operation is little endian | I/o interface, Bit load/store risc architecture, 4k byte instruction ram (1k instructions) per core, 512 bytes data ram per core | Texas Instruments MICROPROCESSOR TI SITARA User Manual | Page 26 / 43
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