HP 9304M - Manual (Page 9)

HP ProCurve Routing Switch 9308M / 9304M Reviewer’s Guide
2.2 Architecture
2.2.1 Hardware Architecture Summary
The HP ProCurve Routing Switch 9304M has 4 identical slots, while the HP ProCurve Routing
Switch 9308M has eight. Any of the modules can be put in any of the slots. The only rule is that there
must be one, and only one, card with the management function installed in the chassis. While there are
managed versions of each of the different modules available (except for the 100Base-FX module), it is
best to have management on a Gigabit card as there is no loss of actual ports. The managed version of
the 10/100 card, on the other hand, has only 16 ports on it compared to the 24 ports on the unmanaged
card.
Each of the modules, which is based on a shared memory structure, is interconnected through a
backplane using a crosspoint matrix interconnect. The crosspoint matrix in the HP ProCurve Routing
Switch 9308M is twice as large as the HP ProCurve Routing Switch 9304M to handle up to double the
number of packets expected from the eight slots versus the four slots in the 9304M.
The HP ProCurve Routing Switch 9304M has two slots for the load-sharing power supplies. One supply
ships with the 9304M and can power a fully loaded chassis. The HP ProCurve Routing Switch 9308M
has four power supply slots available; a minimum of two supplies (supplied) are needed to run a fully
loaded chassis. A third and/or fourth power supply can be installed for redundancy and longer
expected overall power supply life.
Overall, the hardware is designed to provide a non-blocking architecture, so that the HP ProCurve
routing switches can easily sit in the middle of a medium-to-large enterprise campus providing the
traffic-forwarding performance needed.
The HP ProCurve routing switches allow 64,000 MAC addresses. Boot time from a cold start is
<10 seconds.
2.2.2 Packet Processor
Each port on a module has a packet processor associated with it. The packet processor is responsible
for reading into the packet headers so that forwarding decisions can be made based on the Layer 2,
Layer 3, Layer 4 and filtering requirements. The packet processor then generates a forwarding
identifier (FID) that defines destination port, port mirroring requirements, packet type, VLAN
affiliation, prioritization and other parameters. If processor based functions are needed, such as
AppleTalk routing, that is also determined. The packet processor also modifies the bits in the packet as
required for routing, such as time-to-live (TTL), MAC addresses and checksums. If Layer 4 information
is to be processed, that is also determined at this point, with the FID modified as necessary.
Once the FID has been determined for a packet, it is stored in a cache area that is managed by the
management board. Actual movement of the packet through the routing switch data pathways is
specified by the FID, resulting in the packet making it’s way to the proper output port(s) of the routing
switch.
2.2.3 Shared Memory
Modules are based on a shared memory architecture. Packets are buffered on the module in this shared
memory area. The pipeline to/from the packet processors to the shared memory has a 64 Gbps
throughput. The actual data rate through this switch fabric is 32 Gbps, since in shared memory designs
the packet has to travel the fabric twice, once inbound and once outbound. The 32 Gbps is ample, as
the maximum data rate the shared memory will see is 16 Gbps, 8 Gbps from the ports, and 8 Gbps from
the backplane. The packet is managed in shared memory through a shared memory identifier (SMID).
This shared memory area size on the module is 2 to 8 MB, depending on the module type.
©1999 Hewlett-Packard Company Revision 4.0 – 4/1/1999 Page: 9 of 27