Motorola VL-RISC MCF5202 - Manual (Page 11)

MOTOROLA GATEWAY BOARD 11
!BG68K pin 16 istype 'output'; "nBG68K
!BGCF pin 20 istype 'output'; "nBGCF
LDAT pin 22 istype 'output'; "(!nLE16_8) - 0=transparent latches, L-2-H=latches data
!OEBA8 pin 23 istype 'output'; "nOEBA8 =0=HIZ, 1=output from B (TDAT) to A (AD) enabled
!OEAB8 pin 24 istype 'output'; "nOEAB8 =0=HIZ, 1=output from A (AD) to B (TDAT) enabled
!OEBA16 pin 25 istype 'output'; "nOEBA16=0=HIZ, 1=output from B (TDAT) to A (AD) enabled
!OEAB16 pin 26 istype 'output'; "nOEAB16=0=HIZ, 1=output from A (AD) to B (TDAT) enabled
!UDS pin 31 istype 'output'; "nUDS
!LDS pin 32 istype 'output'; "nLDS
!ADLT pin 33 istype 'output'; "Addr Latch - 0=transparent latches, L-2-H=latches data
!AS pin 34 istype 'output'; "nAS
!DA1 pin 35 istype 'output'; "nDA1
!DA0 pin 36 istype 'output'; "nDA0
!AEUP pin 37 istype 'output'; "Addr Enable for A[23:8] - AEUP=0=HIZ, AEUP=1=output
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"Internal Nodes
PQ0,PQ1,PQ2 node istype 'reg, buffer';
A0 node istype 'reg,buffer';
ATMA node istype 'reg,buffer';
NQ1 node istype 'reg';
NQ2 node istype 'reg';
NCLK node;
BQ0,BQ1 node istype 'reg,buffer';
"Constants
c,k,x,z = .C.,.K.,.X.,.Z.; "this is used for test vectors
"State Value Constants
psreg = [PQ2,PQ1,PQ0]; "Positive Clk State Register
PS0 = [0,0,0]; "!PQ2&!PQ1&!PQ0
PS1 = [0,0,1]; "!PQ2&!PQ1&PQ0
PS2 = [0,1,1]; Ò!PQ2&PQ1&PQ0
PS3 = [0,1,0]; "!PQ2&PQ1&!PQ0
PS4 = [1,1,0]; "PQ2&PQ1&!PQ0
PS5 = [1,0,0]; "PQ2&!PQ1&!PQ0
PSTATE0 = !PQ2&!PQ1&!PQ0;
PSTATE1 = !PQ2&!PQ1&PQ0;
PSTATE2 = !PQ2&PQ1&PQ0;
PSTATE3 = !PQ2&PQ1&!PQ0;
PSTATE4 = PQ2&PQ1&!PQ0;
PSTATE5 = PQ2&!PQ1&!PQ0;
bsreg = [BQ1,BQ0]; "BusArb State Register
BS0 = [0,0];
BS1 = [0,1];
BS2 = [1,1];
BS3 = [1,0];
Equations
"Initializations
psreg.clk = PCLK;
psreg.ar = RSTI;
A0.clk = TS; "AD0 is latched when TS is asserted
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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