Maxim Integrated MAX3420E - Manual (Page 4)

9. What does the CONNECT bit do?
The MAX3420E has a switchable internal 1500Ω pullup resistor between its D+ pin and V
CC
.
The CONNECT bit operates this switch. This switch allows a bus- powered peripheral to delay
connection to USB until it finishes initialization. It also allows a self-powered peripheral to
remove V
CC
from the pullup resistor in the absence of V
BUS
, as required by the USB
Specification.
3. Interface Questions
1. How does a microprocessor connect to the MAX3420E?
The microprocessor connects to the MAX3420E by implementing an SPI master, using 3, 4, or
5 wires. Some microcontrollers include hardware SPI, but many do not. In this latter case, it is
easy to implement an SPI master by bit-banging general-purpose IO pins.
2. You say the SPI interface is 3, 4, or 5 wires. What does this mean?
The minimum SPI interface consists of three wires: SS# (Slave Select), SCLK (Serial Clock),
and MISO (configured for bidirectional MISO/MOSI data). Since this interface does not use the
INT pin, the controlling microprocessor would need to poll two interrupt-request registers to
determine when the MAX3420E requires service.
By setting a control bit (FDUPSPI, full-duplex SPI), the MOSI and MISO data appear on
separate pins, providing a 4-wire interface. Finally, an INT (interrupt out) pin can be connected
to a processor's interrupt system.
3. What SPI clocking modes does the MAX3420E support?
The SPI mode is usually expressed in the form (x,y) where one variable is the clock polarity,
CPOL, and the other is the clock phase, CPHA. The MAX3420E operates in modes (0,0) or
(1,1) without requiring a mode bit. The only difference between these modes is the inactive
SCLK level: low for (0,0), high for (1,1). There are two basic requirements for running the
MAX3420E SPI interface:
MOSI data supplied to the MAX3420E must be valid before the first positive SCLK edge.
SPI input data is sampled on the positive edge of the clock, and output data changes on
the negative edge of SCLK.
Be careful with these modes—some microprocessor data sheets do not adhere to the (0,0)
and (1,1) convention. It is best to verify the above two points when setting a clock mode. Also
see the
MAX3420E data sheet and MAX3420E Programming Guide for SPI example
waveforms.
4. My CPU uses a 2.5V supply, but the MAX3420E uses a 3.3V V
CC
supply. Do I need
external level translators?
No. The MAX3420E contains internal level shifters. A V
L
pin powers the internal logic and
serves as the logic reference voltage for the SPI and IO pin signals. For a 2.5V interface,
connect your 2.5V supply to the V
L
pin. The V
L
pin can actually operate with a range of
voltages from 1.7V to 3.6V. If the controller uses 3.3V, tie V
L
to V
CC
.
5. What is the purpose of the MAX3420E INT pin?
The INT pin goes active whenever the MAX3420E requires service. During USB peripheral
operation, this includes the arrival of SETUP, IN or OUT packets, plus bus events like bus
reset, suspend, and resume. Using this pin in a system reduces the SPI traffic since the
interrupt request bits do not need to be polled over the SPI interface.
6. Does the MAX3420E support active-low wired-OR interrupts? How about edge active
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