2 setting up the pll in hardware, 6 verifying correct setup, 1 using the led on the sdp – Motorola ONCE SC140 User Manual
Page 18: Setting up the pll in hardware, Using the led on the sdp, Section 6, “verifying correct setup,” de, 6verifying correct setup
14
Using the SC140 Enhanced OnCE Stopwatch Timer
With these configurations, the Fchip is calculated as expressed in Equation 3.
Eqn. 3
The PLL should be configured so that the resulting PLL output frequency is in the range specified in the
device’s technical data sheet.
5.2
Setting Up the PLL in Hardware
During the assertion of hardware reset, the value of all the PLL hardware configurations pins are sampled
into the clock control registers (PCTL0 and PCTL1). Thus, it is possible to set up the core frequency at
reset by configuring the jumpers on the SDP board.
To set up the PLL for operation at 300 MHz, the jumpers for PLLEN, PDF1, PDF0, MFI3 and MFI2
should be removed (thereby causing these bits to be asserted).
For more detail information jumper configuration of SDP, refers to [2].
6
Verifying Correct Setup
The previous sections described how to set up the Enhanced OnCE stopwatch timer and the DSP clock
speed. This section describes techniques to verify that the system is set up correctly and that the Enhanced
OnCE stopwatch timer measurements are reasonable as described in Section 3, “Setting Up the Stopwatch
Timer Within an Application,” on page -3.
The verification process is based on measuring a specified time period, while also creating an external
behavior (turning on and off an LED) that can be measured independently by a “wall clock” (that is; an
independent stopwatch, such as; an oscilloscope).
6.1
Using the LED on the SDP
The implementation described in this section is based on the configuration of the Software Development
Platform (SDP). In SDP, each of EE1 pins of the Enhanced OnCE is connected to an LED.
The following implementation is based on the ability to program the Enhanced OnCE to toggle the output
value on its pins whenever an event is detected by one of the Enhanced OnCE event detection channels.
The implementation below toggles the output value on the pin EE1 whenever the stopwatch timer starts or
stops running. This capability requires just a small enhancement to the stopwatch timer software that is
presented in Code 6 on page -13.
6.1.1
Setting Up EE1
The functionality of the Enhanced OnCE pins is controlled through the Enhanced OnCE pins control
register (EE_CTRL). Figure 10 displays the structure of this register.
Figure 10. EE Pins Control Register (EE_CTRL)
Fchip
50MHz
24
0
1
---
+
Ч
4
1
Ч
----------------------------------------------
300Mhz
=
=