Marantz SUPER AUDIO CD PLAYER SA8400 User Manual

Page 30

Advertising
background image

3-3

IC502 : CXD1885Q

No.

Terminal Name

I/O

A/D

Classifi cation

Function

PU PD SMT

38 DVSS

P

VDD & GND

Digital Ground.

39 VDT5

O

D

VSTEM A/V

MPEG data output 5.

40 VDT4

O

D

VSTEM A/V

MPEG data output 4.

41 VDT3

O

D

VSTEM A/V

MPEG data output 3.

42 VDT2

O

D

VSTEM A/V

MPEG data output 2.

43 VDT1

O

D

VSTEM A/V

MPEG data output 1.

44 VDT0

O

D

VSTEM A/V

MPEG data output 0.

45 HDRQ

I

D

VSTEM A/V

MPEG data Request input.

*

46 XHAC

O

D

VSTEM A/V

Data Valid output.

47 VEFG

O

D

VSTEM A/V

ECC Error-sector Flag output. (L: error sector)

48 XSHD

O

D

VSTEM A/V

DVD Sector Head Flag output.

49 DCK

O

D

VSTEM A/V

Data Strobe output.

50 DRVIRQ

O

D

VSTEM Command

Interrupt Request output for Host. (L: interruption is demanded)

51 DRVRST

I

D

VSTEM Command

Drive H/W Reset input. (L: reset)

*

*

52 DVDD18

P

VDD & GND

Digital 1.8V power for Internal logic system.

53 DVDD33

P

VDD & GND

Digital 3.3V Power for I/O.

54 DRVTX

O

D

VSTEM Command

Transmitting serial data output to Host.

55 DRVRX

I

D

VSTEM Command

Reception serial data input from Host.

56 DRVCLK

I

D

VSTEM Command

Clock input from Host.

*

57 DRVRDY

O

D

VSTEM Command

Drive Ready signal output. (L: ready)

58 C2PO

O

D

Audio I/F

CD-DSP C2 Pointer output.

59 DADT

O

D

Audio I/F

Audio serial data output.

60 DOTX

O

D

Audio I/F

Digital audio output.

61 LRCK

O

D

Audio I/F

L/R Clock output.

62 BCK

O

D

Audio I/F

Audio Bit Clock output.

63 EXVCO

I

D

TEST/Monitor

External Channel clock input.

64 EXPLDT

I

D

TEST/Monitor

External RF data input. (Logic level)

65 CSL

O

D

ASP I/F

SIO for RF signal processing LSI control. Latch signal output.

66 SI

I

D

ASP I/F

SIO for RF signal processing LSI control. Serial data input.

67 SO

O

D

ASP I/F

SIO for RF signal processing LSI control. Serial data output.

68 SCLKH

O

D

ASP I/F

SIO for RF signal processing LSI control. Serial clock output.

69 RFOKGH

I

D

ASP I/F

RF O.K. Signal input.

*

70 HFD

I

D

ASP I/F

RF lack Signal input.

*

71 MIRRORH

I

D

ASP I/F

Mirror detected signal input.(H: Mirror detected)

*

72 DTC

I

D

ASP I/F

Track cross signal input. (Logic level input)

*

73 AVSS

P

VDD & GND

Analog Ground.

74 ATC

I

A

Data PLL

Track Cross signal input. (Analog level input)

75 HF

I

A

Data PLL

RF signal input.

76 TLC0

O

A

Data PLL

Asymmetry Charge-pump output 0.

77 TLC1

O

A

Data PLL

Asymmetry Charge-pump output 1

78 IREF

I

A

Data PLL

Reference current setting terminal for Asymmetry Circuit.

79 AVDD33

P

VDD & GND

Analog 3.3V Power.

80 JMREF

I

A

Data PLL

Reference current setting terminal for Jitter Monitor

81 JMOUT

O

A

Data PLL

Jitter Monitor output.

82 CHG

I

A

Data PLL

Reference current setting terminal for data PLL.

83 VFBC

I

A

Data PLL

VCO offset frequency setting terminal for data PLL.

84 AVDD18

P

VDD & GND

Analog 1.8V Power.

85 VCOI

I

A

Data PLL

VCO Control voltage input terminal for data PLL.

86 LPF1

O

A

Data PLL

VCO Loop-fi lter connection terminal 1 for data PLL.

87 LPF2

O

A

Data PLL

VCO Loop-fi lter connection terminal 2 for data PLL

88 RC

I

A

Data PLL

VCO gain setting terminal for data PLL.

89 AVSS

P

VDD & GND

Analog Ground.

90 AVSS

P

VDD & GND

Analog Ground.

91 AD0

I

A

ADC

AD0 Input.

92 AD1

I

A

ADC

AD1 Input.

93 AD2

I

A

ADC

AD2 Input.

94 AVDD33

P

VDD & GND

Analog 3.3V Power.

95 AD3

I

A

ADC

AD3 Input.

96 AD4

I

A

ADC

AD4 Input.

97 AD5

I

A

ADC

AD5 Input.

98 AD6

I

A

ADC

AD6 Input.

99 AD7

I

A

ADC

AD7 Input.

100 AD8

I

A

ADC

AD8 Input.

101 AD9

I

A

ADC

AD9 Input.

Advertising