Control diagnostic registers – Maxtor DIAMONDMAX PLUS 40 54098U8 User Manual

Page 39

Advertising
background image

HOST SOFTWARE INTERFACE

6 – 5

Control Diagnostic Registers

Control Diagnostic Registers

Control Diagnostic Registers

Control Diagnostic Registers

Control Diagnostic Registers

These I/O port addresses reference three Control/Diagnostic registers:

T

R

O

P

O

/

I

D

A

E

R

E

T

I

R

W

h

6

F

3

s

u

t

a

t

S

e

t

a

n

r

e

tl

A

l

o

rt

n

o

C

k

s

i

D

d

e

x

i

F

h

7

F

3

t

u

p

n

I

l

a

ti

g

i

D

d

e

s

u

t

o

N

Alternate Status Register

Alternate Status Register

Alternate Status Register

Alternate Status Register

Alternate Status Register

Contains the same information as the Status register in the Task File. However, this register may be read at
any time without clearing a pending interrupt.

Device Control Register

Device Control Register

Device Control Register

Device Control Register

Device Control Register

Contains the software Reset and Enable bit to enable interrupt requests to the host. Bit definitions follow:

7

6

5

4

3

2

1

0

0

0

0

0

0

T

S

R

S

N

E

I

0

t

e

s

e

R

e

l

b

a

n

E

Q

R

I

Reset

– Setting the software Reset bit holds the drive in the reset state. Clearing the bit re-enables the drive.

The software Reset bit must be held active for a minimum of 5 µsec.

IRQ Enable

– Setting the Interrupt Request Enable to 0 enables the IRQ 14 signal to the host. When this

bit is set to 1, IRQ14 is tri-stated, and interrupts to the host are disabled. Any pending interrupt occurs when

the bit is set to 0. The default state of this bit after power up is 0 (interrupt enabled).

Digital Input Register

Digital Input Register

Digital Input Register

Digital Input Register

Digital Input Register

Contains information about the state of the drive. Bit definitions follow:

7

6

5

4

3

2

1

0

x

G

W

-

3

S

H

-

2

S

H

-

1

S

H

-

0

S

H

-

1

S

D

-

0

S

D

d

e

v

r

e

s

e

R

e

t

a

G

d

a

e

H

3

t

c

e

l

e

S

d

a

e

H

2

t

c

e

l

e

S

d

a

e

H

1

t

c

e

l

e

S

d

a

e

H

0

t

c

e

l

e

S

e

v

ir

D

1

t

c

e

l

e

S

e

v

ir

D

0

t

c

e

l

e

S

Bit 7 of the host data bus is not driven when this register is read.

-Write Gate

– Reflects the state of the active low write gate signal on the drive.

-Head Select 3 through -Head Select 0

– Represents the ones complement of the currently selected head number.

-Drive Select 1

– Is 0 if drive 1 selected; 1 otherwise.

-Drive Select 0

– Is 0 if drive 0 selected; 1 otherwise.

Advertising