Intel Xeon - Manual (Page 27)

Intel ® Xeon™ Processor, Intel ® E7520 Chipset, Intel ® 6300ESB ICH Development Kit User’s Manual 27
System Overview
5.3 Platform Resets
Figure 7 depicts the reset logic for the CRB. The Intel 6300ESB I/O Controller provides most of
the reset following assertion of power good and system reset. However, the glue logic within the
SIO is also used to buffer reset to PXH, MCH, FWH, and IDE.
Figure 7. Platform Reset Diagram
B2938-03
Intel
®
6300ESB
I/O
Controller
Hub
MCH Port 80
PCI-E
SYS_PWRGD_3V3
CPURST#
SYS_RESET#
PCIRST_N
PXH_PAPCIRST_N
PCIRST2# PCIRST1#
VRM_PWRGD
IDERST#
PCI-X
PCI-X
PCI 32
FWH
CPU 1
CPU 0
ITP-700
PXH_PBPCIRST_N
PCI-X
PCI-X
PCI-X
SIO IDE
PXH