3 power manager pll configuration register (ppcr), System control module – Intel STRONGARM SA-1100 User Manual
Page 105
SA-1100 Developer’s Manual
9-35
System Control Module
9.5.7.3
Power Manager PLL Configuration Register (PPCR)
The PPCR contains bits used to configure the core operating frequency generated by the PLL. The
following table shows the bit-field definitions for this register. See
for the
frequencies generated through settings in this register. Note that the contents of this register are
preserved during sleep mode and do not need to be re-initialized after a wake-up event. The PPCR
is only cleared upon the assertion of nRESET (hard reset).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
Reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
Reserved
CCF
4
CCF
3
CCF
2
CCF
1
CCF
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
4-0
CCF<4:0>
Clock speed configuration.
See
for the values in this field.
31..5
—
Reserved.