Document Outline

• 1.0 Introduction
  • 1.1 Functional Overview
    • Figure 1. 82555 10/100 Mbps Ethernet Solution
  • 1.2 Compliance to Industry Standards
• 2.0 Architectural Overview
  • Figure 2. 82555 Simplified Block Diagram
  • 2.1 100 Mbps Mode
    • Figure 3. 82555 Analog Logic
  • 2.2 10 Mbps Mode
    • Figure 4. Intel 82557/82555 Solution
  • 2.3 Media Independent Interface (MII)
    • Table 1. 82555 MII
• 3.0 Pin Definitions
  • Figure 5. 82555 Pin Numbers and Labels
  • 3.1 Pin Types
  • 3.2 Clock Pins
  • 3.3 Twisted Pair Ethernet (TPE) Pins
  • 3.4 Media Independent Interface (MII) Pins
  • 3.5 Media Access Control/Repeater Interface Control Pins
  • 3.6 LED Pins
  • 3.7 External Bias Pins
  • 3.8 Miscellaneous Control Pins
  • 3.9 Power and Ground Pins
• 4.0 100BASE-TX Adapter Mode Operation
  • 4.1 100BASE-TX Transmit Clock Generation
  • 4.2 100BASE-TX Transmit Blocks
    • 4.2.1 100BASE-TX 4B/5B Encoder
      • Table 2. 4B/5B Encoder
    • 4.2.2 100BASE-TX Scrambler and MLT-3 Encoder
      • Figure 6. NRZ to MLT-3 Encoding Diagram
    • 4.2.3 100BASE-TX Transmit Framing
    • 4.2.4 Transmit Driver
      • Figure 7. Conceptual Transmit Differential Waveform
      • Table 3. Magnetics Modules
  • 4.3 100BASE-TX Receive Blocks
    • 4.3.1 Adaptive Equalizer
    • 4.3.2 Receive Clock and Data Recovery
    • 4.3.3 MLT-3 Decoder, Descrambler, and Receive Digital Section
    • 4.3.4 100BASE-TX Receive Framing
    • 4.3.5 100BASE-TX Receive Error Detection and Reporting
  • 4.4 100BASE-TX Collision Detection
  • 4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution
    • 4.5.1 Link Integrity
    • 4.5.2 Auto-Negotiation
    • 4.5.3 Combination Tx/T4 Auto-Negotiation Solution
      • Figure 8. Combination Card Example
  • 4.6 Auto 10/100 Mbps Speed Selection
  • 4.7 Adapter Mode Addresses
• 5.0 10BASE-T Functionality in Adapter Mode
  • 5.1 10BASE-T Transmit Clock Generation
  • 5.2 10BASE-T Transmit Blocks
    • 5.2.1 10BASE-T Manchester Encoder
    • 5.2.2 10BASE-T Driver and Filter
  • 5.3 10BASE-T Receive Blocks
    • 5.3.1 10BASE-T Manchester Decoder
    • 5.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter
    • 5.3.3 10BASE-T Error Detection and Reporting
  • 5.4 10BASE-T Collision Detection
  • 5.5 10BASE-T Link Integrity
  • 5.6 10BASE-T Jabber Control Function
  • 5.7 10BASE-T Full Duplex
• 6.0 Repeater Mode
  • 6.1 Special Repeater Features
  • 6.2 Connectivity
    • Figure 9. Clock Signal Example
• 7.0 Management Data Interface
  • 7.1 MDI Frame Structure
  • 7.2 MDI Registers
    • 7.2.1 MDI Registers 0 - 7
      • 7.2.1.1 Register 0: Control Register Bit Definitions
      • 7.2.1.2 Register 1: Status Register Bit Definitions
      • 7.2.1.3 Register 2: 82555 Identifier Register Bit Definitions
      • 7.2.1.4 Register 3: 82555 Identifier Register Bit Definitions
      • 7.2.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions
      • 7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions
      • 7.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
    • 7.2.2 MDI Registers 8 - 15
    • 7.2.3 MDI Registers 16 - 31
      • 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions
      • 7.2.3.2 Register 17: 82555 Special Control Bit Definitions
      • 7.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
      • 7.2.3.4 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
      • 7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions
      • 7.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions
      • 7.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
      • 7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
      • 7.2.3.9 Register 27: 82555 Special Control Bit Definitions
• 8.0 Auto-Negotiation Functionality
  • 8.1 Description
    • Table 4. Technology Ability Field Bit Assignments
    • Table 5. Technology Priority
  • 8.2 Parallel Detect and Auto-Negotiation
    • Figure 10. Auto-Negotiation and Parallel Detect
• 9.0 LED Descriptions
• 10.0 Reset and Miscellaneous Test Modes
  • 10.1 Reset
  • 10.2 Loopback
  • 10.3 Scrambler Bypass
  • 10.4 Test Port
    • Table 6. Test Instruction Coding
• 11.0 Electrical Specifications and Timing Parameters
  • 11.1 Absolute Maximum Ratings
  • 11.2 General Operating Conditions
  • 11.3 DC Characteristics
    • 11.3.1 MII DC Characteristics
    • 11.3.2 10BASE-T Voltage/Current DC Characteristics
      • Figure 11. RBIAS10 Resistance versus ICCT10
    • 11.3.3 100BASE-TX Voltage/Current DC Characteristics
      • Figure 12. RBIAS100 Resistance versus ICCT100
  • 11.4 AC Characteristics
    • Figure 13. AC Testing Level Conditions
    • 11.4.1 MII Clock Specifications
      • Figure 14. MII Clocks AC Timing
    • 11.4.2 MII Timing Parameters
      • Figure 15. MII Transmit Timing Parameters
      • Figure 16. MII Receive Timing Parameters
      • Figure 17. MII Timing Parameters: MDC/MDIO
    • 11.4.3 Repeater Mode Timing Parameters
      • Figure 18. PORT Enable Timing
    • 11.4.4 Transmit Packet Timing Parameters
      • Figure 19. Transmit Frame Timing Parameters
    • 11.4.5 Squelch Test Timing Parameters
      • Figure 20. Squelch Test Timing Parameters
    • 11.4.6 Jabber Timing Parameters
      • Figure 21. Jabber Timing Parameters
    • 11.4.7 Receive Packet Timing Parameters
      • Figure 22. Receive Packet Timing Parameters
    • 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters
      • Figure 23. Normal Link Pulse Timing Parameters
    • 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
      • Figure 24. Fast Link Pulse Timing Parameters
    • 11.4.10 Reset Timing Parameters
      • Figure 25. Reset Timing Parameters
    • 11.4.11 X1 Clock Specifications
      • Figure 26. X1 Clock Specifications
    • 11.4.12 100BASE-TX Transmitter AC Specification
• 12.0 82555 Package Information
  • Figure 27. Dimension Diagram for the 82555 QFP
  • Table 7. Dimensions for the 82555 QFP