Intel 386 - Manual (Page 386)

12-51
DMA CONTROLLER
with BP=0 causes the DMA to set BP. The clear byte pointer software command
(DMACLRBP) allows you to force BP to a known state (0) before writing to the registers.
• The target and requester addresses are incremented, decremented, or left unchanged and the
byte count is decremented after each data transfer within a buffer transfer. Reading a
register returns the current (or modified) value rather than the original programmed values.
• The chaining buffer-transfer mode requires that you write new transfer information to the
channel before the current buffer transfer completes. The channel determines whether new
transfer information was written to it by checking the most-significant byte of the target
address. Writing to this byte sets an internal flag that tells the channel that new transfer
information was written to it. Therefore, it is only necessary to change the target address
between chaining buffer transfers. If you want to change the requester address and byte
count also, you should write these values before writing the most-significant byte of the
target address.
• If a channel is configured to increment the requester address and the requester’s bus size is
selected as 16 bits, the channel increments the requester address by two after each data
transfer. However, if the channel is configured to decrement the requester address, the
channel only decrements the address by one. This is true for the target also. In other words,
the channels cannot decrement by words. When a channel is configured to decrement the
requester or target address and transfer words, the correct number of words is transferred;
however, the transfers are on a byte basis.
• Enabling both the autoinitialize and chaining buffer-transfer modes will have unpredictable
results.
• The DMA controller does not allow programming one channel while another channel is
active. If both channels are being used, the programmer must mask an active channel before
reprogramming the other channel. Failure to do this may result in incorrect DMA transfers.
12.5.1 DMA Controller Code Examples
This section contains these software routines:
EnableDMAHWRequests Enables channel hardware requests for the given
DMA channel
DisableDMAHWRequests Disables channel hardware requests for the specified
DMA channel
SetDMAReqIOAddr Sets the requester to an I/O port address for the
specified channel
SetDMATargMemAddr Sets the target memory address for the specified DMA
channel
SetDMAXferCount Sets the target memory device for the specified DMA
channel
InitDMA Initializes the DMA