Intel 80303 - Manual (Page 8)

Summary Table of Changes
8 Intel ® 80303 and 80302 I/O Processors Specification Update
Errata
No.
Steppings
Page Status Errata
A-0 A-1 A-2
1 X X X 12 NoFix
Single-bit and Multi-bit Error Reporting Cannot Be
Individually Enabled by ECC Control Register
2 X X X 12 NoFix
Instruction Sequence Can Scoreboard a Register
Indefinitely
Specification Changes
No.
Steppings
Page Status Specification Changes
A-2 #-# #-#
1 X 14 Doc Summary of the Intel® 80302 I/O Processor
Specification Clarifications
No.
Steppings
Page Status Specification Clarifications
A-0 A-1 A-2
1 X X X 15 Doc ECC is Always Enabled
2 X X X 15 Doc 32-bit SDRAM is Not Supported
3 X X X 15 Doc Non-Battery Backup Systems
4 X X X 15 Doc POCCDR and SOCCDR Functionality
5 X X X 15 Doc ‘Bus Hold’ Devices on the RAD Bus
6 X X X 16 Doc SREQ64# Functionality
7 X X X 16 Doc PCI Local Bus Specification, Revision 2.3 Compliancy
8 X X X 16 Doc DMA and AAU End of Chain Functionality