Samsung S3C8275X - Manual (Page 125)

INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
5-8
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Source Interrupt Level Register(s) Location(s) in Set 1
Timer B match
Timer 1/A match IRQ0 TBCON, TBDATA, TBCNT
TACON, TADATA, TACNT E7H, E5H, E3H, bank 1
E6H, E4H, E2H, bank 1
SIO interrupt IRQ1 SIOCON
SIODATA
SIOPS E1H, bank 0
E2H, bank 0
E3H, bank 0
Watch timer overflow IRQ2 WTCON E1H, bank 1
P0.0 external interrupt IRQ3 P0CONL
EXTICONL
EXTIPND E5H, bank 0
F9H, bank 0
F7H, bank 0
P0.1 external interrupt
IRQ4 P0CONL
EXTICONL
EXTIPND
E5H, bank 0
F9H, bank 0
F7H, bank 0
P0.2 external interrupt IRQ5 P0CONL
EXTICONL
EXTIPND E5H, bank 0
F9H, bank 0
F7H, bank 0
P1.3 external interrupt IRQ6 P1CONL
EXTICONL
EXTIPND E8H, bank 0
F9H, bank 0
F7H, bank 0
P1.7 external interrupt
P1.6 external interrupt
P1.5 external interrupt
P1.4 external interrupt IRQ7 P1CONH
EXTICONH
EXTIPND
E7H, bank 0
F8H, bank 0
F7H, bank 0
NOTE: If an interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.