SUPER MICRO Computer H8QMI-2 - Manual (Page 58)

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H8QM3-2/H8QMi-2 User’s Manual
ECC Confi guration
DRAM ECC Enable
DRAM ECC allows hardware to report and correct memory errors automati-
cally. Options are Enabled and Disabled.
4-Bit ECC Mode
Allows the user to enabled 4-bit ECC mode (also known as ECC
Chipkill). Options are Enabled and Disabled.
DRAM Scrub Redirect
Allows system to correct DRAM ECC errors immediately, even with
background scrubbing on. Options are Enabled and Disabled.
DRAM BG Scrub
Corrects memory errors so later reads are correct. Options are Dis-
abled and various times in nanoseconds and microseconds.
L2 Cache BG Scrub
Allows L2 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
Data Cache BG Scrub
Allows L1 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
Power Down Control
Allows DIMMs to enter power down mode by deasserting the clock enable signal
when DIMMs are not in use. Options are Auto and Disabled.
Alternate VID
Specifi es and alternate VID while in low power states. Options are Auto and
various voltages between .8V and 1.115V.
Memory Timing Parameters
Allows the user to select which CPU Node's timing parameters (memory clock,
etc.) to display. Options are CPU Node 0, CPU Node 1, CPU Node 2 and CPU
Node 3.