SMC Networks SMC91C95 - Manual (Page 121)

121
FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES
t20
A0-15
AEN,
nSBHE
nIOCS16
nIOWR
D0-D15
VALID ADDRESS
VALID ADDRESS
nIORD
t9
t10
Z Z Z
VALID DATA VALID DATA
IOCHRDY
Z Z
Control Active to IOCHRDY Low
IOCHRDY Low Pulse Width*
Cycle time**
Parameter min typ max units
100
185
15
150
ns
ns
ns
t9
t10
t20
*Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
**Note: The cycle time is defined only for accesses to the Data Register as follows:
For Data Register Read - From nIORD falling to next nIORD falling
For Data Register Write - From nIOWR rising to next nIOWR rising